IBM unveils Nanostack transistor architecture targeting sub-1nm scaling in 2030s for next-generation chips.

IBM has developed a sub-nanometer chip technology it claims could be used to produce commercial chips within five years, with a mapped path to 0.1 nm. The company says its new process node can cram nearly 100 billion transistors onto a silicon die the size of a fingernail—almost double the density of the 2 nm technology it unveiled in 2021.

The new process is engineered for 0.7 nm (7 Angstroms), compared with the cutting-edge manufacturing nodes being prepared for production in 2028 by Intel and TSMC at 1.4 nm (14 Angstroms). Several structural and material innovations underpin this latest method, including a three-dimensional nanostack architecture that stacks transistors with n-type and p-type field-effect transistors arranged in vertical layers.

"We're announcing it's not just an incremental step, it's a meaningful leap forward, enabling up to 50 percent higher performance, or 70 percent greater efficiency [than 2 nm], and pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy," said Jay Gambetta, director of IBM Research and IBM Fellow. The firm sees a clear path to shrinking down to one-tenth of a nanometer over the next decade. "Nanostack is not one innovation. It is actually a device platform that can enable the future of scaling for another decade beyond nanosheet, as you can see from our technology roadmap all the way to 1 Angstrom."

Though IBM touts nanostack as the industry's first three-dimensional, nanosheet-based design, Intel discussed 3D transistor stacking in 2023 without implementing it, and Huawei developed a similar concept in its LogicFolding architecture using two fused wafers. IBM's design has a distinctive twist: transistors in the upper layer are staggered or offset from those below.

"What happens here is we actually stack in vertical direction but also stagger, so the front side of each transistor and the backside of each transistor can be contacted independently for signal and power," explained Huiming Bu, VP of Silicon Technology Research & Development at IBM. "The stacking of this transistor is done by single dielectric bonding, which is a key innovation that we have developed. Through that technology, the channel materials—essentially the top FET and the bottom FET—can be optimized independently."

IBM says the architecture could support multiple applications including CPUs, GPUs, mobile chips, and memory such as SRAM. Gambetta suggested the technology could power future AI accelerators. "This is why we were excited by the initial experiment that shows a 40 percent scaling in SRAM. There are many examples of AI chips that are using more SRAM to scale, but fundamentally, it comes down to: can we make transistors more efficient, less power, put more in there?" he said.

IBM no longer manufactures chips itself. When asked which foundry might adopt its sub-nanometer process, Bu noted that the nanosheet architecture IBM invented is now used by all leading foundries. "I'm not going to talk about a business model, but it's being adopted by all leading foundries. But today, we are focusing on helping Rapidus to be successful in bringing up 2 nm manufacturing capability in Japan," he stated. Rapidus is a government-backed semiconductor foundry established to revitalize Japan's semiconductor industry.

The nanostack transistor architecture is detailed in a paper available from the IEEE.