Alphabet is financially backing both Nvidia’s NVLink Fusion and AMD’s UALink to hedge against interconnect vendor lock-in.
The day NVIDIA announced a $3.5 billion investment in Taiwan’s MediaTek, binding the chip designer into its NVLink Fusion ecosystem, another investor quietly joined the same bond offering: Alphabet. The disclosure was easy to miss—MediaTek’s statement listed Alphabet alongside “other investors” without specifying dollar amounts, as confirmed by CNBC’s September 2026 coverage—but it proves to be the most analytically significant detail in a deal that drew enormous attention focused almost entirely on the wrong question.
The conventional framing of the NVIDIA-MediaTek deal asks whether AI infrastructure will standardize on NVLink Fusion, NVIDIA’s proprietary interconnect, or UALink, the open standard backed by AMD, Intel, Google, Microsoft, Meta, and roughly 85 other companies. That framing assumes the two paths are mutually exclusive and that hyperscalers must choose sides. Alphabet’s co-investment in the MediaTek bond offering is the clearest evidence available that this premise is flawed.
Alphabet is a founding member of the UALink Consortium alongside AMD, Broadcom, Cisco, HPE, Intel, Meta, and Microsoft, and helped draft the UALink specification. Simultaneously, it is paying MediaTek to design the TPU v8i (codename Zebrafish)—Google’s cost-optimized AI inference chip—through a design partnership announced at Google Cloud Next 2026. Then, on August 31, 2026, Alphabet co-invested alongside NVIDIA in the $3.9 billion MediaTek convertible bond offering that formalized MediaTek as NVLink Fusion’s primary XPU integration gateway for hyperscalers. Alphabet is actively engaged on all three sides of a supposedly binary competition. This is not confusion; it is a deliberate portfolio strategy, and it is the critical signal that TechTimes readers building or procuring AI infrastructure must understand before committing to any interconnect architecture.
The mechanics of NVIDIA’s investment matter because they reveal what the company is actually optimizing for. NVIDIA purchased convertible bonds—not equity—representing approximately 90% of MediaTek’s record $3.9 billion offering, the largest of its kind in Taiwan’s capital market history. Convertible bonds pay a fixed return (or, in some structures, zero coupon) while granting the holder the right to convert into equity at a predetermined price. NVIDIA’s financial return appreciates most if MediaTek’s stock rises, which occurs if MediaTek’s AI chip business grows, which in turn depends on hyperscalers using MediaTek to design custom accelerators that connect into NVLink Fusion. The financial instrument and the technology strategy are identical bets.
In exchange, NVIDIA secured MediaTek’s commitment to offer NVLink Fusion as the design foundation for custom AI accelerators—called XPUs—that MediaTek builds on behalf of hyperscalers and other large customers. When a hyperscaler brings a custom compute die to MediaTek for production, it receives a chip pre-equipped with NVIDIA’s UCIe bridge chiplet, which links the custom silicon to NVIDIA’s NVLink fabric without requiring the customer’s engineering team to independently master NVIDIA’s proprietary interconnect specification.
The agreement also deepens prior collaborations between the two firms. MediaTek co-designed the GB10 Grace Blackwell Superchip at the core of NVIDIA’s DGX Spark personal AI supercomputer, contributing the CPU cores and memory controller while NVIDIA supplied the GPU die and the NVLink chip-to-chip interconnect. Future generations of both DGX Spark and RTX Spark—NVIDIA’s Arm-based computing platform for Windows laptops targeting consumers and developers—will continue to be developed jointly under a roadmap outlined in NVIDIA’s official announcement. Jensen Huang, NVIDIA’s founder and CEO, called MediaTek “one of the world’s great semiconductor companies.” MediaTek vice chairman and CEO Rick Tsai described the investment as strengthening a relationship “spanning cloud AI infrastructure, local AI computing, and automotive in the era of physical AI.”
Understanding what hyperscalers gain—and surrender—when adopting NVLink Fusion requires examining the platform’s three architectural layers. At the die-to-die level, custom accelerators and XPUs connect to NVIDIA’s fabric through a UCIe bridge chiplet. UCIe (Universal Chiplet Interconnect Express) is an open industry standard for die-to-die communication within a package. NVIDIA’s NVLink Fusion chiplet receives UCIe signals from the custom die on one side and translates them to NVLink protocol on the other, allowing chip designers to work in the open UCIe standard while NVIDIA’s proprietary protocol remains encapsulated within the chiplet. The custom compute die never needs to implement NVLink directly.
At the chip-to-chip level, NVLink-C2C delivers bidirectional bandwidth of 300 gigabytes per second for connections between CPUs and GPUs or CPUs and XPUs, matching the interconnect used in the GB10 SoC. At the rack level, NVIDIA’s sixth-generation NVLink switch fabric connects up to 72 XPUs in a single all-to-all domain at 3.6 terabytes per second per XPU, yielding an aggregate bandwidth of 260 terabytes per second across the full domain and end-to-end latency three times lower than Ethernet, as documented in NVIDIA’s developer blog.
What NVIDIA does not share are the NVLink Switch chips themselves, the PHY layers, and the communication controllers that regulate the fabric. Every XPU in the NVLink Fusion ecosystem must connect to an NVIDIA product to access the network. The platform is open to custom compute dies but closed to custom switching. This architectural choice is NVIDIA’s economic requirement for participating in the custom silicon economy: it ensures that even when a hyperscaler substitutes NVIDIA GPUs with its own custom chips, NVIDIA still captures revenue from the switch trays, ConnectX NICs, BlueField DPUs, or Vera CPUs deployed in the same rack.
Moor Insights analyst Matt Kimball, vice president and principal analyst at Moor Insights and Strategy, plainly identified the viable options: scale-up Ethernet, NVLink Fusion, and UALink. For hyperscalers evaluating their path, those three routes remain, but production realities significantly narrow the practical choice.
NVIDIA also announced a new memory architecture alongside the AWS Trainium4 partnership on August 26—one week before the MediaTek deal—that extends its proprietary influence from the interconnect layer into the memory subsystem. NVHBM (NVIDIA High-Bandwidth Memory) relocates the HBM memory controller from the XPU’s compute die and embeds it directly into the HBM base die, the foundational layer of the three-dimensional memory stack.
In every AI accelerator built to today’s JEDEC HBM4e standard, the logic managing communication between the processor and its memory stacks resides on the processor die, consuming silicon area that could otherwise host compute units. NVHBM eliminates this constraint by moving the controller into the memory package itself. According to NVIDIA’s NVHBM architectural specifications, this yields a 67% reduction in PHY and interface area on the XPU compute die, up to 25% more compute die area available for differentiated logic, 30% greater memory bandwidth versus standard HBM4e, and 15% lower HBM power consumption, resulting in a stated 30% improvement in end-to-end XPU performance.
At data center scale, these power savings compound. A facility operating at one gigawatt with 2,000-watt accelerators could theoretically accommodate approximately 15,000 additional XPUs within the same power envelope solely through NVHBM’s memory efficiency—adding compute capacity not by increasing power draw, but by allocating memory power more effectively.
Amazon’s Annapurna Labs, which designs the AWS Trainium custom AI training chip series, is the first announced partner collaborating on NVHBM for Trainium4. Under this arrangement, Trainium4 silicon will connect into the same NVLink fabric as NVIDIA GPUs, enabling rack-scale systems where AWS-designed accelerators and NVIDIA chips operate side by side over a common high-bandwidth fabric. AWS is simultaneously a founding board member of UALink. It is pursuing both architectures, just as Alphabet is.
One caveat for procurement teams: as of September 2026, every NVHBM performance specification remains an architectural figure from NVIDIA, not a measurement from a shipping product. As of September 2026, no independent NVHBM benchmarks exist. AWS’s early collaboration provides an external signal that at least one major customer has evaluated and fo