Marvell has boosted the capacity and speed of its CXL-connected memory with AI workloads in mind.

Marvell has upgraded its CXL memory expansion controllers to make more memory available for AI key-value (KV) caching workloads. When a GPU's high-bandwidth memory runs out of capacity for the cached key-value items used in AI token processing, the cache can spill down to the server's x86 DRAM, which also has capacity limits. Compute Express Link (CXL) pools external memory and makes it available across the PCIe bus to connected servers and other devices, enlarging the DRAM KV caching pool. The original Structera CXL controllers, which supported CXL 2.0 and PCIe Gen5, have been upgraded to support CXL 3.2 and PCIe Gen6, along with more memory channels.

Will Chu, EVP and GM of Custom Cloud Solutions at Marvell, said: "Marvell is the only provider with a complete end-to-end CXL portfolio spanning memory expansion (Structera X), near-memory acceleration (Structera A), and PFMA (Photonic Fabric Memory Appliance), pod-scale CXL memory-sharing appliance, giving customers a complete portfolio from direct-attach to disaggregated memory pooling. We are delivering industry-leading CXL controllers, co-developed with leading hyperscalers to address the most demanding AI infrastructure requirements."

Marvell's first-generation Structera controllers were the X 2404 and X 2504. The second generation comprises the X 3406 and X 3506. The naming scheme works as follows:

- **First digit:** CXL generation (2 = CXL 2.0; 3 = CXL 3.x / 3.2)

- **Second digit:** DDR generation (4 = DDR4; 5 = DDR5)

- **Last two digits:** Memory channel count (04 = 4 channels; 06 = 6 channels)

The X 3406 and X 3506 provide the following:

- **Expanded memory capacity for AI:** Six DDR4/DDR5 memory channels, 50 percent more than the previous generation, supporting up to 9TB of DDR4 or 6TB of DDR5 memory per controller.

- **Accelerated memory-bound AI workloads:** Up to 5x higher LZ4 compression throughput enables 2–3x more effective memory capacity, helping improve large language model serving and DLRM (Deep Learning Recommendation Model) performance.

- **More hosts:** CXL 3.2 support enables memory sharing across up to four hosts with up to 256 GB/s of host bandwidth, combined with enterprise-grade RAS and post-quantum security.

Jim Handy, general director of Objective Analysis and author of a CXL market report, said: "CXL is starting to gain widespread adoption in AI systems since they reap strong benefits from its very high bandwidth and support of large memory sizes. In addition, today's memory shortage and subsequent high prices are driving IT managers to use CXL to re-deploy used DDR4 DIMMs into DDR5 systems for immediate cost savings. In the near future, these same managers will use CXL's memory pools to reduce stranded memory and drive greater savings, and they will find controllers that offer compression, as this one does, to be even more interesting."

Marvell said the prior-generation X 2404/2504 architecture is "already shipping to hyperscalers," and two hyperscalers have offered support for the new generation.

An Alibaba spokesperson said: "Our collaboration with Marvell brings together its leadership in CXL technology with Alibaba's experience in large-scale AI and cloud infrastructure to develop memory architectures designed for the next generation of AI data centers."

Yashar Bayani, Meta director of Hardware Engineering, said: "Meta is pleased to work with Marvell to advance CXL solutions that address the growing memory demands of compute infrastructure. As systems scale, increasing memory capacity while improving infrastructure efficiency and cost becomes critical. CXL provides a flexible approach to expanding memory resources and optimizing infrastructure economics, and we look forward to working with the ecosystem, including Marvell, to help enable the next generation of scalable infrastructure."

The Marvell Structera X 3406 and Structera X 3506 CXL memory expansion controllers are expected to sample in Q1 2027.

Marvell has a strong focus on photonics, and we expect it to introduce external memory pools connected to processors across high-speed photonic links. CXL will likely adapt to photonics mainly by using optical interconnects (silicon photonics and fiber) as the physical transport layer while keeping the CXL protocol, coherency, and memory semantics intact. PCIe at Gen6 and Gen7 could also adopt photonics physical transport.