Marvell introduced Radix and Teralynx T100, a low-latency, high-bandwidth interconnect ASIC targeting next-generation AI and HPC data center architectures.
Modern high-performance computing and artificial intelligence systems demand a careful balance among three critical networking parameters: high switch radix—the number of ports available on a given switch ASIC—combined with low latency and high bandwidth. Marvell, which acquired the hyperscale Ethernet chip startup Innovium in August 2021, has been pushing these boundaries since Innovium's founding in 2015. With the new Teralynx T100, sampling any day now, Marvell's switch ASIC team is pursuing all three vectors simultaneously, positioning the chips for adoption by hyperscalers, cloud builders, and AI model developers seeking high-bandwidth, high-radix, low-latency Ethernet for both scale-out and scale-up networks.
The Teralynx product line has grown dramatically since 2020. Innovium shipped more than 1 million 400 Gb/sec Ethernet ports using its Teralynx 7 and 8 chips that year. By 2022, Marvell had expanded the product line into mass production with ASICs ranging from 12.8 Tb/sec to 51.2 Tb/sec of aggregate bandwidth. By 2023, over 5 million 400 Gb/sec ports had shipped—representing more than 300,000 switches. By 2025, Marvell had delivered more than 20 million 400 Gb/sec ports, equivalent to approximately 1.25 million switches, driven largely by the 51.2 Tb/sec Teralynx 10 ASIC that ramped in 2024 on TSMC's 5-nanometer process.
The T100 pushes further still. According to Rishi Chugh, general manager of Marvell's Network Switching Division, the new ASIC is a monolithic design pushed to the reticle limits using TSMC's 3-nanometer process. It delivers 100.4 Tb/sec of aggregate bandwidth using 224 Gb/sec SerDes, which operate at 200 Gb/sec after signaling overhead. The design wraps 512 working SerDes around packet processing engines and SRAM cache. By maintaining a monolithic die rather than splitting SerDes into chiplets, the T100 achieves 25 percent lower power consumption than an alternative chiplet approach—a trade-off accepting higher cost and yield challenges on the relatively new N3 process. The actual die carries 19 percent more SerDes than specified, compensating for these yield pressures.
Typical power consumption stays under 1,000 watts, and the chip achieves port-to-port hop latency of 420 nanoseconds. While this exceeds InfiniBand's approximately 130 nanoseconds at equivalent port speeds, Marvell is targeting latency in the middle 300-nanosecond range with further optimization—low enough to support ESUN's scale-up memory sharing protocol for AI accelerators as an alternative to Nvidia's NVLink and NVSwitch memory fabric.
The T100 supports Ultra Ethernet Consortium protocols, including adaptive routing for scale-out networks spanning tens to hundreds of thousands of accelerators. Like its predecessors, it runs SONiC, the open-source Linux-derived network operating system originally created by Microsoft, as well as custom network operating systems from hyperscalers and cloud builders.
The 512 working SerDes can be configured flexibly: 512 ports at 200 Gb/sec, 256 ports at 400 Gb/sec, 128 ports at 800 Gb/sec, or 64 ports at 1.6 Tb/sec.
Marvell is offering three packaging variants. BGA reference platforms deliver 64 ports at 1.6 Tb/sec in a 3U form factor: one following the Open Compute Project's Open Rack v3 standard with bus bar power supply and 21-inch width—suggesting Meta Platforms as a potential user—and a conventional 19-inch, 3U form factor with AC power supplies. Both sample in Q4 2026. For co-packaged copper deployments, Marvell provides a 2U switch with 64 OSFP ports at 1.6 Tb/sec with CPC connectivity, and a 1U variant with 24 ports. The co-packaged optics variant follows the Open Rack v3 design with DC bus bar and optional AC power, featuring Compute on Module Express control-plane support for either X86 or Arm processors, with initial designs combining air and liquid cooling—though full liquid cooling is expected for production deployments.
Total cost of ownership benefits include substantial capital and operational savings at volume deployment scale, with one analysis suggesting $200 million in TCO savings. Marvell expects ESUN-based T100 switches in the second half of 2027, with Microsoft and Meta Platforms reportedly among major supporters. UALink switches are planned for the first half of 2027.