At Hot Chips 2026, XCENA demonstrated its MX1 device combining a CXL memory controller with 3072 RISC-V cores and SSD tiering, while Samsung showcased scaling its LPDDR5X-PIM solution.

XCENA is presenting its MX1 CXL computational memory device at Hot Chips 2026 in a joint session with Samsung, pairing the chip with a rack-scale CXL memory architecture. The MX1 is a Type 3 CXL component that integrates three capabilities into a single package: CXL memory expansion, SSD-backed storage exposed as byte-addressable CXL memory, and near-memory processing across thousands of RISC-V cores. Building on prior coverage of the first-generation MX1 as a CXL 3.0 computational memory part, this session expands the technology’s scope to rack-scale systems.

XCENA’s central thesis is that AI workloads bottleneck on memory capacity, bandwidth, and power efficiency long before they reach limits in raw compute. The MX1 addresses these constraints through four DDR5-8400 channels supporting up to 2TB of CXL memory expansion. Additionally, an SSD connected to the MX1 root port is exposed to the host as fully addressable CXL memory. Near-memory compute is delivered via 3,072 custom RISC-V cores integrated directly onto the die.

Fabricated on Samsung Foundry’s 4nm process, the MX1 die is partitioned into 24 subsystems. Each subsystem comprises four clusters of 32 Memory Units (MUs), totaling 3,072 MUs. XCENA defines the subsystem as the fundamental unit of host job allocation; each can execute independent workloads while sharing a 128MB L3 cache.

XCENA opted for numerous simple in-order RISC-V cores rather than fewer high-performance cores, aligning with the bandwidth-bound and power-sensitive nature of target workloads. This architecture enables the integration of 3,072 cores while maintaining low energy consumption per byte. The open RISC-V ISA offers a mature development toolchain and supports custom instructions tailored for data-parallel tasks, including in-memory analytics, Retrieval-Augmented Generation (RAG) retrieval, and memory compression.

A Vector Processing Engine supplements the scalar MUs with dedicated vector execution paths. Each MX1 SoC achieves approximately 3 TFLOPS of peak dot-product throughput, supporting operations including element-wise arithmetic, reductions, CRC32, and vector-scalar computations. Dedicated per-MU command queues are optimized for RAG vector search and KV cache scoring.

On-chip locality is carefully managed. Each cluster features an 8KB L1 instruction cache shared across four MUs and a 256KB L2 data cache shared among its 32 MUs. A 128MB Last-Level Cache (LLC) interconnects the clusters. Instruction fetching utilizes physical addresses, while data accesses rely on host virtual addresses, with address translation coordinated at the cluster level.

A critical software design choice involves implementing a unified virtual address space shared between the host and the MUs. By allowing the host and device to reference identical pointers, pointer-intensive data structures traverse safely, and legacy `malloc`-based applications can migrate to CXL memory with minimal refactoring. A CXL-aware allocator maintains per-tenant page tables to isolate application kernels and memory allocations.

On the software stack, XCENA provides PXL (Parallel Xceleration Library), a MapReduce-style runtime. PXL manages the application lifecycle from device context initialization through kernel definition in C/C++ or Rust. It handles job scheduling across one or more subsystems and exposes a map API that distributes work across MU cores, automating memory allocation and synchronization.

XCENA reports throughput improvements of up to 4.7x compared to host-over-CXL configurations and 2x versus local DRAM, while consuming approximately one-quarter of the host’s power. These metrics translate to efficiency gains of up to 18.7x over CXL and 6.2x over DRAM. Benchmarks were conducted using an Intel Xeon 6767P reference platform, with idle power excluded from measurements.

Extending beyond DRAM, the MX1 exposes SSD capacity as byte-addressable CXL memory through XCENA’s “Infinite Memory” architecture. This DRAM-and-NAND hybrid leverages onboard DRAM to cache SSD pages. Data is segmented into 64KB pages, managed by a 1,024-entry map cache TLB, with cache misses serviced by firmware executing on the MU cores. While conceptually similar to established memory tiering solutions, XCENA’s implementation integrates tightly with the CXL fabric. The approach underscores the industry’s continued reliance on NAND-backed caching layers following the discontinuation of Intel Optane.

Infinite Memory directly addresses KV cache management in generative AI workloads. When a prompt prefix is pinned to resident memory, XCENA demonstrates query Time-To-First-Token (TTFT) performance within 1.13x of native DRAM. Removing the pin increases latency to 1.57x, while a raw SSD baseline reaches 1.86x. A lookahead prefetch mechanism, which capitalizes on device underutilization, restores performance to near-DRAM levels. Benchmarks utilized Llama-3.1-8B with vLLM, LMCache, and an NVIDIA RTX 6000 Pro GPU.

The latter portion of the session highlights Samsung’s processing-near-memory research leveraging the MX1. Samsung’s methodology emphasizes exploiting the high DRAM bandwidth available behind the CXL interconnect by performing computations in situ and transferring only aggregated results. Presentations contrasted DDR5 bandwidth at 268.8 GB/s against a 64 GB/s PCIe Gen6 x8 host link, reflecting the current rollout timeline for Gen6 server processors. During the session, Samsung noted that CXL adoption is accelerating across major hyperscalers, particularly for database acceleration and AI/KV cache workloads.

Samsung and XCENA outlined a rack-scale CXL computational memory architecture enabling GPU servers to pool memory via CXL semantics. The reference configuration integrates a Liqid CXL switch with GPU servers equipped with 96GB NVIDIA RTX Pro 6000 Blackwell accelerators, targeting 20TB of aggregate memory capacity and 2.7 TB/s of sustained bandwidth.

To facilitate software integration, Samsung introduced the NDC API, a vendor-agnostic near-data-computing library open-sourced via the OCP Foundation’s FTI DCC initiative. PyTorch compatibility is achieved through OpenXLA and the PrivateUse1 backend, enabling AI frameworks to interface directly with the XCENA PXL runtime without requiring application-level modifications.

Samsung demonstrated two primary AI workloads. The first focuses on RAG vector search using CXL-accelerated PNM with FAISS IVF Flat indexing. Because L2 k-nearest neighbors distance calculations are heavily memory-bandwidth-bound, Samsung offloaded the operation to the MX1 devices. Deploying 10 PNM units yielded 64x higher queries per second and 65x improved query-per-energy efficiency compared to a host CPU paired with a standard CXL memory pool, utilizing a 512-million-vector FAISS index derived from the LAION-5B dataset.

The second workload targets LLM decoding via GPU-plus-PNM hybrid attention. In this architecture, frequently accessed (“hit”) KV cache pages remain on the GPU, while evicted (“miss”) pages are routed to the PNM device. Rather than transferring entire KV pages back to the host, the PNM unit computes and returns only the resulting attention scores. Decode timelines compare traditional GPU-only attention loading KV caches from CXL against this hybrid offloading strategy.

Samsung highlighted significant performance gains on the hybrid decode path. Operating at a 100K context window, the PNM pool increased throughput by 3.35x and token-per-energy efficiency by 3.84x, achieving 17.7 versus 5.50 tokens per second and 4.31 versus 1.12 tokens per kilojoule, respectively. Benchmarks executed LLaMA-3.1-70B in INT8 precision across two servers, each configured with five MX1 devices and NVIDIA RTX Pro 6000 Blackwell GPUs.

Collectively, XCENA and Samsung are positioning the MX1 as production-ready silicon central to the computational memory paradigm. The partnership integrates the accelerator, the PXL runtime, and Infinite Memory caching with Samsung’s rack-scale pooling infrastructure.

XCENA’s presentation reinforces the argument that memory capacity, bandwidth, and efficiency—not raw compute—remain the primary bottlenecks for AI and analytics workloads. The proposed solution relocates optimization logic from the host CPU or GPU into a dedicated CXL device. By combining near-memory RISC-V compute, SSD-backed byte-addressable storage, and Samsung’s rack-scale pooling, the architecture establishes a new memory tier capable of scaling both capacity and processing power in tandem. The practical validation of this integrated approach, alongside its SSD tiering implementation, will be closely monitored as the technology matures.