NVIDIA presented CUDA integration with RISC-V controllers and NVLink Fusion systems at Hot Chips 2026.
NVIDIA took the stage at Hot Chips 2026 to detail RISC-V integration with its GPU ecosystem. While initial coverage of several RISC-V presentations during the Sunday tutorial session lagged, this report synthesizes the key architectural disclosures. Notably, this session diverged from NVIDIA’s other Hot Chips presentations, featuring a distinct opening sequence tailored to its tutorial format.
The presentation was structured around two primary platforms: CUDA and NVLink Fusion. Each defines a specific role for host CPUs, with NVIDIA outlining the requirements RISC-V processors must satisfy, alongside the opportunities and challenges of expanding its software stack to RISC-V. CUDA, introduced in 2006 as a parallel computing platform, remains central to how NVIDIA envisions integrating RISC-V into its broader compute architecture.
CUDA applications divide work between CPU and GPU software modules. Compute-intensive functions are parallelized across the GPU, while sequential operations execute on the host CPU. This host-side software stack is inherently complex and heterogeneous, mixing CPU-only and CUDA-accelerated components atop CUDA libraries, drivers, development tools, and third-party software tailored to the target architecture. NVIDIA currently supports Intel and AMD x86 processors, as well as Arm-based CPUs, on the host side.
For RISC-V CPUs to run CUDA workloads, NVIDIA points to established server-related specifications. The RVA23 profile and the RISC-V Boot and Runtime Services specification address the application layer, while broader RISC-V server SoC and platform specifications define system-level requirements. Binary compatibility is a primary objective; the RVA23 profile guarantees the presence of key extensions, enabling software to run across diverse RISC-V processors without requiring a lowest-common-denominator approach. Despite perceptions of RISC-V as fragmented, the RISC-V International organization continues to release major and minor updates that clearly delineate mandatory and optional new extensions.
ACPI serves as a concrete example of these platform requirements. The UEFI Forum added RISC-V support to ACPI 6.6, which was ratified in May 2025, followed by the RISC-V Boot and Runtime Services specification in August 2025. These standards were formalized just over a year ago, underscoring the rapid pace of platform maturation.
CUDA workloads depend heavily on data movement between host and device memory. A typical operation involves host-to-device transfers, kernel execution, device-to-host transfers, and intervening CPU processing. To optimize this, NVIDIA highlights PCIe coherency as a critical CUDA-specific requirement, noting its adoption across most, if not all, modern server CPUs. Hardware-based PCIe I/O coherence eliminates frequent cache flush and invalidate operations, simplifying software stacks and reducing latency.
PCIe peer-to-peer communication represents another CUDA-specific requirement. In multi-GPU configurations, a GPU can write data directly into another GPU’s device memory and signal the host via flags, bypassing unnecessary copies through host memory. This capability explains the unconventional server architectures observed in GPU deployments even a decade ago.
The Vera Rubin platform exemplifies NVIDIA’s full-stack AI factory approach, engineered through co-design across seven chips and five racks. Spanning from the Vera CPU and Rubin GPU through networking, storage, and scale-out fabric to the physical rack infrastructure, this architecture has proven foundational enough to be referenced repeatedly throughout the conference.
Within the NVL72 rack, NVIDIA consolidates a 72-GPU L1 domain into a fully copper interconnect topology. Each compute tray houses GPUs mounted on NVLink Fusion chiplets, paired with two Vera CPUs and Chip-to-Chip (C2C) links connecting the processors to the accelerators. While NVIDIA’s Grace and Vera Arm-ISA-based CPUs power this configuration, the underlying platform design extends far beyond a single ISA.
NVLink Fusion enables custom silicon to integrate seamlessly into NVIDIA’s AI platform. Custom CPUs attach to XPUs via NVLink C2C, delivering high-bandwidth connectivity to each accelerator while maintaining a unified L1 domain across the entire rack. Inside a custom CPU, NVIDIA detailed the C2C interface integration, where an NVLink C2C PHY provides a high-bandwidth, CHI-coherent CPU-to-GPU link. This architecture allows both CPU and GPU to access memory under a unified memory model.
NVLink Fusion CPUs inherit all CUDA prerequisites and introduce additional demands. NVIDIA emphasized a high-speed C2C interconnect supporting approximately 88 PCIe lanes, alongside specialized software ecosystems including DOCA for networking and NCCL for multi-GPU communication. These specifications are rarely discussed in public forums, making this segment particularly notable. SiFive was explicitly identified as NVIDIA’s RISC-V-based partner for NVLink Fusion CPUs.
NVIDIA concluded by advocating for RISC-V’s role in next-generation server platforms. As an open standard supported by multiple vendors, RISC-V—combined with standardized core features and customizable extensions—expands server CPU options alongside x86 and Arm. “NVIDIA has plans for RISC-V in its platforms,” the presentation confirmed. It is worth noting that NVIDIA already utilizes RISC-V in current systems for lower-level controllers, though this session specifically addressed host processor integration.
Collectively, these architectural details illustrate how NVIDIA envisions RISC-V fitting within both CUDA and NVLink Fusion ecosystems. The company’s roadmap clearly positions RISC-V as a viable third option in the server CPU market. Published requirements, ranging from RVA23 compliance to NVLink Fusion integration, will dictate the performance and feature sets that RISC-V server silicon must deliver to qualify for future GPU platforms. While broader deployment may still be two generations away, industry consensus confirms that RISC-V’s entry into high-performance server computing is inevitable.