At Hot Chips 2026, Intel detailed its Crescent Island AI accelerator built on the Xe3P architecture, which utilizes liquid-cooled chips to maximize AI FLOPS per watt.

At the Hot Chips 2026 symposium, Intel provided deeper architectural insights into its Crescent Island AI accelerator, which is built on the Xe3P architecture. Unlike Nvidia’s Rubin and AMD’s MI455X GPUs—high-power, exclusively liquid-cooled chips that rely on massive HBM4 memory pools to deliver peak performance across both AI training and inference workloads—Crescent Island targets a lower-power, inference-first segment of the AI accelerator market. The chip is designed as a 350W air-cooled PCIe card capable of supporting up to 480 GB of LPDDR5X memory, allowing deployment in traditional server environments without requiring specialized power or cooling infrastructure.

Crescent Island is constructed from four Xe3P slices, each containing eight Xe Cores for a total of 32. Every Xe Core integrates eight Xe Vector Engines and eight XMX matrix accelerators, resulting in 256 vector engines and 256 XMX units across the entire die. To sustain these compute resources, Intel has significantly expanded the cache hierarchy. Each Xe Core now features 1 MB of general-purpose register file space, doubling the 512 KB capacity found in Battlemage and Xe2 architectures. Additionally, Xe3P provides 512 KB of L1 cache or shared local memory per Xe Core, up from 256 KB on Battlemage and representing approximately a 1.33x increase over Panther Lake’s Xe3 GPU. The chip also includes a 32 MB shared L2 cache, all engineered to efficiently feed the chip’s larger matrix accelerators.

A key architectural advancement lies in the XMX engines, which utilize a 16-deep systolic design. This allows the chip to process matrices in substantially larger chunks than the four-deep systolic designs employed in Xe2 and Xe3. While Nvidia does not publicly disclose comparable architectural specifics for its Tensor Cores, this increased parallelism delivers a meaningful capability boost for concurrent matrix-multiply operations during AI inference. Intel has also prioritized broad data type support, spanning from FP4 formats with microscaling (MXFP4) to full-rate double-precision computing via 64 FP64 FMA units per Xe Core. Although FP64 is rarely utilized in standard AI workloads, Intel states that full-rate support positions Crescent Island as a viable converged platform for both high-performance computing and AI applications. Each Xe Core also supports sigmoid and tanh transcendental functions, which are critical for operations like softmax, aligning with capabilities recently emphasized by AMD and Nvidia in their own AI-focused architectures.

Crescent Island includes a media codec block featuring four encoders and decoders to assist multimodal AI models with video processing. However, the chip deliberately omits graphics-specific features such as ray tracing cores to maximize die area for compute functionality, meaning it will not serve as a foundation for future consumer Arc graphics products. As a data-center-grade component, it incorporates comprehensive reliability, availability, and serviceability features, including ECC and parity protection across the die alongside various memory reliability mechanisms.

Intel specifically highlights mixture-of-experts models paired with speculative decoding as a primary target workload. Speculative decoding employs lightweight mechanisms to generate draft tokens that the main model subsequently accepts or rejects, improving overall decode efficiency. Much like speculative execution in CPUs, this approach extracts useful computation from otherwise idle resources, even if not every draft token is approved. As model-serving strategies adopt more aggressive drafting techniques, the computational demand for generating these drafts increases, shifting the traditional perception of decode from a primarily memory-bandwidth-bound operation to a compute-heavy one. Because Crescent Island relies on LPDDR5X rather than HBM, it lacks the extreme bandwidth of competing accelerators for traditional autoregressive decode. Consequently, leveraging speculative decoding becomes essential to maximizing throughput.

Intel emphasizes that Crescent Island is engineered for high FLOPS per watt and optimized for compute-bound phases of AI inference, particularly prefill operations such as prompt processing and KV cache construction. This focus suggests a complementary role alongside HBM-backed accelerators better suited for decode-heavy workloads. Such a disaggregated approach could benefit partnerships like the one with SambaNova, whose SN50 inference accelerators are explicitly designed to leverage GPU-powered prefill processing. Both SN50 racks and Crescent Island are positioned as lower-power, air-cooled systems deployable in existing data centers without major infrastructure upgrades, creating strong ecosystem synergy. While Intel has not yet disclosed specific theoretical FLOPS or memory bandwidth figures, the architectural strategy of keeping data close to compute engines and processing larger batches within a narrow power envelope appears strategically sound as the company works to reset its AI ambitions following a string of high-profile product failures and cancellations. Crescent Island is slated for release in the second half of 2026, with industry observers awaiting final specifications and early customer adoption metrics upon launch.