Intel showcased Diamond Rapids, its 2027 Intel Xeon server CPU featuring up to 256 cores per socket, at Hot Chips 2026.

Intel presented Diamond Rapids, its next-generation Xeon server platform, on day one of Hot Chips 2026. Serving as the follow-on to Xeon 6 “Granite Rapids,” Diamond Rapids represents a central component of Intel’s data center roadmap. The platform, now designated as the Xeon 7 “Diamond Rapids” series, has been rescheduled for a 2027 launch following a timing adjustment made earlier this year. Notably, the 256-core configuration was integrated into the roadmap very recently. Looking ahead, Intel’s next-generation Coral Rapids remains a substantial family that will likely be showcased at Hot Chips 2027.

The presentation opened by establishing four foundational pillars for the platform: performance efficiency, acceleration, scalability, and security. Intel outlined the architectural lineage leading to Diamond Rapids, tracing a path from monolithic ring and mesh designs through the disaggregated 2.5D tile partitions of Sapphire Rapids and Granite Rapids, to the current generation’s 2.5D and 3D function partitions. This progression positions Diamond Rapids at the apex of Intel’s modular design trajectory.

At the heart of the platform lies a set of scalable compute building blocks centered around a Fabric Hub. Each hub centralizes memory and I/O resources, allowing compute blocks to connect via a unified memory fabric and a flexible I/O fabric. Every compute building block chiplet connects directly to the fabric hub, which itself is designed for scalability. Within each compute block, core chiplets contain up to 16 cores each and link to a last-level cache on a base tile through a 3D crossbar. This cache is shared across the entire compute block, with Intel scaling both the number of core chiplets per base tile and the total compute blocks per chip.

Intel refers to the interconnect as the Flexbus I/O fabric, supported by a unified memory fabric delivering up to 1.6 TB/s of bandwidth. To maintain efficiency, snoop filtering and home agents reside on-die, keeping cache coherence localized to the fabric rather than spanning the entire platform. Memory interfaces through a dedicated controller within the Fabric Hub, scheduling DDR with robust ECC, power management, and row-hammer protection. The subsystem also supports CXL memory in either one-level or flat two-level modes with mirroring, while a dedicated memory encryption engine secures both DDR and CXL pathways. Each Fabric Hub provides four x16 ports configurable as PCIe Gen6, CXL 3, or UPI 3. These hubs also feature up to 16 MB of I/O cache with on-die snoop filtering, alongside two accelerator complexes housing QAT, DSA, and IAA engines.

Power management is engineered at the compute building-block level. Intel introduced a new core idle state featuring L2 cache retention, priority-core turbo support, MR4-based memory thermal management, and low-power L0p support across both UXI and PCIe links. Physically, the flagship package stacks two Fabric Hub tiles, 16 core chiplets, and four base tiles. Core chiplets interface with the base tile via a hybrid bonding connection using Foveros 3D direct die-to-die technology, while substrate copper links route interconnects to the Fabric Hub tiles.

Built on Intel’s 18A-P process node, the platform leverages an expanded library of low-power and high-performance transistors. Key enhancements include a dual-contact PowerBoost option, a new logic threshold setting between ULVT and LVT, and 33 percent tighter skew corners. On the instruction set architecture front, Intel is introducing spill-and-fill optimization instructions. This update adds 16 general-purpose registers, bringing the total to 32 integer registers, introduces new encodings for registers r16 through r31, and implements three-operand instructions. The changes remain fully backward-compatible with existing x86 software, requiring only recompilation without source modifications.

Coherence management has also been optimized at the silicon level. By replacing DRAM-resident directory state with an on-die snoop filter, Intel eliminates directory storage from main memory. This shift preserves full ECC protection while reducing latency and significantly cutting coherence traffic. Combined with these architectural advances, the flagship configuration delivers 256 cores, 1.28 GB of last-level cache, 1.6 TB/s of memory bandwidth, and 128 lanes of high-bandwidth, low-latency I/O. Acceleration capabilities are handled through AMX and AVX 10.2, featuring expanded vector instruction support. These memory speeds build on the Gen 2 MRDIMM and DDR5-8000 modules previously displayed by STH.

Diamond Rapids positions Intel to compete directly in the high-core-count, high-memory-bandwidth server segment as it approaches its 2027 launch window against aggressive pushes from AMD’s EPYC lineup. The recent roadmap update aligns Intel’s core count with AMD’s 256-core design, which utilizes an all-P-core architecture with 512 threads. Moving coherence on-die, implementing 3D stacking, and transitioning to the 18A-P process node collectively aim to narrow the efficiency gap with competing architectures. Given the current development cycle, Diamond Rapids is expected to reach the market in the second half of 2027.