CXMT가 마이크론의 4F² DRAM 관련 소송에 답변했으며, 첫 4F² 샘플을 연말까지 출하할 예정이라고 밝혔다.

ChangXin Memory Technologies (CXMT) has responded to Micron's argument that the 4F² DRAM cell layout brings no real density gain. In an investor relations record published on October 31, CXMT said its next process platform, the sixth generation, is built on 4F² and has already passed engineering-sample verification, according to Yicai. The first 4F² product will sample to customers by the end of this year, and volume production will follow customer validation and market demand.

The dispute concerns what limits DRAM bit density. At the company's technology webinar on October 21, Micron President and Chief Technology and Products Officer Scott DeBoer said Micron will stay on the 6F² path and develop 3D DRAM instead. He said Micron had studied 4F² for more than 20 years and found no workable scaling path, and he called parts of the 4F² debate a smokescreen. In his view, capacitor pitch and capacitor size, not the transistor layout, set the theoretical density limit.

CXMT did not dispute the physics. It described higher bit density as a complex system problem, in which word lines, bit lines and capacitor structures all compete for space. At a given node, it said, each architecture carries its own cost curve in process integration complexity, number of lithography steps and thermal budget. Memory makers choose differently based on their technology history, existing fab lines, patent portfolios and spending structure, and the company said those choices deserve understanding and respect.

Samsung and SK hynix are also still developing 4F², according to a November 1 analysis published by QQ News. Samsung showed a 16Gb 4F² prototype at ISSCC 2026 that combines vertical channel transistors with wafer-to-wafer hybrid copper bonding. It plans to use 4F² across its 10a, 10b and 10c nodes before moving to 3D DRAM at 10d. Samsung semiconductor CTO Song Jai-hyuk said on October 12 that 4F² work continues. SK hynix is pursuing a vertical-gate approach that it says improves bit density by more than 20%. It verified read and write operations on test arrays in July and plans to present a capacitorless 4F² paper at IEDM in December.

CXMT's version uses what the analysis calls a Vertical Surrounded Gate (VSG) transistor. The company says it has worked on 4F² since its founding and holds more than 300 published patent families on the technology. Because 4F² increases density by changing the cell layout rather than shrinking line widths, it reduces the area factor from 6 to 4 at dimensions that DUV lithography can reach. CXMT has said a DDR5 RDIMM combining 4F² with hybrid bonding will arrive around year-end. The analysis cautions that server modules face strict reliability requirements, so the first generation will mainly serve to validate the technology.