Google는 올해 기밀 AI용 TPU 8tx와 2칩 구성의 TPU 8i Max를 추가했으며, 이는 올해 출시한 세 번째와 네 번째 TPU 시스템이다.

**Key points**

- TPU 8tx uses the same silicon as the TPU 8t training chip, paired with 5th Gen AMD EPYC CPU hosts, and keeps data and model weights isolated during processing [1].

- TPU 8i Max packs two TPU 8i chips into one package, doubling compute, SRAM, and HBM bandwidth versus TPU 8i in the same rack footprint [1].

- Both are reconfigurations of existing silicon, giving Google four TPU systems announced in 2026 [1][3].

- Google says TPUs now serve nearly 100 customers, including frontier labs, trading firms, retailers, and universities, but did not name them [1].

- Google gave no general-availability date, pricing, or regions for either system [1][5].

Google added two systems to its eighth-generation Tensor Processing Unit line on Monday: TPU 8tx, a confidential-computing system that runs Google's training silicon alongside AMD processors, and TPU 8i Max, which combines two inference chips in one package for long-context work [1]. With the TPU 8t and TPU 8i unveiled at Google Cloud Next in April, Google now has four TPU systems announced in one year, which it called a first [1].

Amin Vahdat, Google's chief technologist for AI and infrastructure, said TPUs now serve nearly 100 customers across frontier labs, trading firms, retailers, and universities [1]. Google did not name them and did not give an availability date, pricing, or regions for the new systems [1][5].

**TPU 8tx: training silicon in a secure enclave**

TPU 8tx uses the same silicon as TPU 8t, the training chip, paired with 5th Gen AMD EPYC CPU hosts [1]. Google built it for governments and regulated enterprises that want to run frontier or proprietary models and agents on sensitive data, with hardware-level protection that keeps data and model weights isolated while they are processed [1][2]. Data in use normally has to be decrypted in memory, which is the gap confidential computing closes [3].

Google positions the system for inference and small-scale training on a single box. Customers can fine-tune on private data, distill large models into smaller ones, and train agents with reinforcement learning without moving data between clusters [1][2]. It runs on Boardfly, the low-latency network Google built for TPU 8i. Google claims up to 2x lower latency than TPU 8t, with a near-zero performance penalty from the security features [1][3]. Google published no absolute latency or throughput figures.

**TPU 8i Max: two inference chips per package**

TPU 8i Max places two TPU 8i chips on a single package, doubling compute, on-chip SRAM, and high-bandwidth-memory (HBM) bandwidth relative to TPU 8i, and fitting twice the silicon into the existing rack footprint [1]. Google aims it at workloads where memory is the bottleneck, such as many agents working across a large codebase or hours of video [3], and at the million-token context windows its Gemini models support [2].

Google's April specifications give the baseline: each TPU 8i carries 288 GB of HBM, 384 MB of SRAM, and 8,601 GB/s of HBM bandwidth [4]. Google did not publish absolute figures for the Max package.

| System | Announced | Built for | Silicon / host |

|---|---|---|---|

| TPU 8t | April 2026 | Large-scale pre-training | 216 GB HBM, 128 MB SRAM per chip; 9,600-chip superpods |

| TPU 8i | April 2026 | Low-latency serving and reasoning | 288 GB HBM, 384 MB SRAM, 8,601 GB/s HBM bandwidth per chip |

| TPU 8tx | Nov. 9, 2026 | Confidential inference, small-scale training | TPU 8t silicon with 5th Gen AMD EPYC CPU hosts |

| TPU 8i Max | Nov. 9, 2026 | Long-context and multi-agent inference | Two TPU 8i chips in one package |

**Packaging over new chips**

Neither system is a new chip. Google is changing packaging, networking, memory, and security around existing silicon. Vahdat described TPUs as modular building blocks within its AI Hypercomputer that let Google reconfigure systems quickly [1][3]. Google said it uses its AlphaChip system and Gemini to speed up chip layout [1].

The April chips have not yet shipped broadly. Google said then that TPU 8t and TPU 8i would be generally available later in 2026, claiming up to 2x better performance per watt than the previous Ironwood generation [6].

**The software push against Nvidia**

Much of the announcement targets the software lock-in that keeps customers on Nvidia GPUs. Google open-sourced TorchTPU last month so that PyTorch and Hugging Face models run natively on TPUs, and added TPU backends for the vLLM and SGLang serving frameworks [1]. It also previewed a TPU agent suite that plugs into Claude Code, Cursor, and Google Antigravity to handle onboarding, bottleneck diagnosis, and kernel tuning, and released an open-source XLA Serving Engine that serves models across TPUs, GPUs, and CPUs [1]. Google said Cloud Pathways and dynamic slicing are now generally available on Google Kubernetes Engine, claiming up to 5x faster job startup and, for the latter, 4.5x faster fault recovery [1].

The new hardware closes gaps rather than opening a lead. Nvidia already offers confidential computing on its GPUs and has strengthened its inference line through a licensing and acqui-hire deal with Groq [3]. Google is also spending heavily on the data centers that will house its TPUs, including a $17 billion campus in Cheyenne and a $15 billion Malaysian commitment. Last week, it backstopped Anthropic's Kentucky lease with TeraWulf.

**Sources**

[1] Google (Amin Vahdat), "Our newest TPUs: 8tx and 8i Max, built for the agentic er…"

[2] SiliconANGLE, "Google advances agentic AI custom silicon expanding TPU family wi…"

[3] The Decoder, "Google ships four TPU variants in one year as it ramps up competit…"

[4] Google Cloud, "TPU 8t and TPU 8i technical deep dive" (April 22, 2026)

[5] TestingCatalog, "Google adds TPU 8tx and TPU 8i Max for AI workloads" (Nov. 9, 2026)

[6] Google, "Our eighth generation TPUs: two chips for the agentic era" (April 22, 2026)