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Inference chip startup d-Matrix announced that its Raptor memory-based XPU will integrate with Nvidia's Rackscale Iron platform via Nvidia's NVLink Fusion interconnect for rack-scale AI inference.

Integration with Nvidia's ecosystem and platform demonstrates inference accelerator traction and offers customers an alternative to Nvidia's native H-series for specific inference workloads.
Trade pressSlicast · September 10, 2026 at 15:06 UTC · US · Source: Crypto Briefing
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Building your own AI chip is hard—getting it into production racks at scale is arguably harder. D-Matrix, an inference-focused semiconductor startup, has announced a shortcut: its next-generation Raptor XPUs will connect directly into NVIDIA's NVLink Fusion interconnect, gaining access to the entire rack-scale infrastructure NVIDIA has spent years perfecting.

Under the partnership, Raptor accelerators will connect through NVIDIA's sixth-generation NVLink fabric and slot into MGX reference architecture racks. Initial Raptor-based MGX systems are projected for 2027, with first units expected in Q4.

NVLink Fusion, introduced by NVIDIA in 2025, allows third-party XPUs and CPUs to tap into NVLink's low-latency links without building their own networking stack from scratch. The integration supports rack-scale configurations accommodating up to 144 Raptor accelerators within a single all-to-all NVLink domain. Each connection delivers 3x lower XPU-to-XPU latency compared to traditional Ethernet interconnects, with each XPU accessing up to 3 TB/s of bandwidth through the sixth-generation NVLink fabric.

D-Matrix CEO Sid Sheth emphasized that the collaboration accelerates deployment for ultra-low-latency inference use cases—coding assistants, chatbots, and voice agents. The company positions Raptor systems to work alongside NVIDIA's GPU-based racks, handling disaggregated inference workloads.

D-Matrix shipped its prior-generation Corsair XPU beginning in November 2024. Following a $450 million funding round, the company carried a $2 billion valuation. Raptor chips are currently in final design stages, with completion targeted for the end of 2026. The multi-year product roadmap with NVIDIA indicates this is a sustained collaboration that will evolve across future chip generations, not a one-off integration.

D-Matrix has also aligned with Astera Labs for tailored connectivity solutions within the NVLink Fusion framework.

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Inference chip startup d-Matrix announced that… · Slicast