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Microsoft unveiled Maia 300, a chip designed for multi-gigawatt deployments.

Maia 300's multi-gigawatt design target signals Microsoft's push to reduce reliance on Nvidia for inference capacity, reshaping procurement across the AI server supply chain.
Trade pressSlicast · October 12, 2026 at 14:39 UTC · US · Source: Techzine Global
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Microsoft is introducing Maia 300, the third generation of its proprietary AI accelerator. Starting in 2027, the company plans to roll out the Maia family at multi-gigawatt scale, and Maia will then become the primary inference hardware for its products and services. According to Microsoft, Maia 300 delivers 40 percent more tokens per megawatt than GPU systems.

Microsoft designed Maia 300 for AI workloads that the company says are now growing in importance, including long-context reasoning, latency-sensitive conversations, and multi-step agentic tasks. In a full configuration with 96 accelerators, the system achieves up to seven times the token throughput per rack of Maia 200.

Maia 200 is already in production. When Microsoft unveiled it, the chip was built on TSMC's 3nm process and featured 216 GB of HBM3e, 7 TB/s of bandwidth, and 750 watts of power consumption. Maia 200 now powers Microsoft Copilot and supports the MAI team in developing new models. GitHub Copilot and Microsoft Foundry will follow before the end of this year. The chip runs OpenAI models, Microsoft's own MAI models, and open-source models. Anthropic also plans to run Claude models on Maia.

Microsoft is rolling out Maia 200 in the United States, Europe, and Australia. According to the company, for the AI features in Teams, Copilot, and Cowork, the chip delivers up to 1.7 times more tokens per watt than GPU infrastructure.

Memory as a key focus

With Maia 300, the emphasis is not on raw computing power. "Moving data efficiently, rather than raw compute power, is increasingly the bottleneck in large inference systems," Microsoft writes. That is why the chip features a software-defined dataflow architecture, and the AI itself optimizes the kernels.

The specifications are impressive. Eight HBM4 stacks deliver 18 TB/s of memory bandwidth at a 950-watt TDP, more than double that of Maia 200, while power consumption increases by 200 watts. In addition, on-die SRAM serves as a software-managed scratchpad.

Maia 300 consists of multiple chiplets, with separate chiplets for compute, memory controllers, and I/O. TSMC manufactures the compute chiplets using its N2P process. The chip also supports low-precision formats, such as an enhanced version of MXFP4. As a result, the KV cache requires less memory, and context windows can be larger.

A single rack contains 96 accelerators and consumes 167 kilowatts. Together, they offer 27.6 TB of HBM capacity and 1.7 PB/s of aggregate bandwidth. For scale-up, Microsoft uses its own Ethernet-based AI transport protocol, which can scale from a single rack to an entire data center. The first production rollout is scheduled for 2027.

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Microsoft unveiled Maia 300, a chip designed… · Slicast