IBM announces sub-1 nanometer chip technology using NanoStack architecture, achieving 100 billion transistors in fingernail-sized space with 40% SRAM density improvement

IBM has developed what it calls the world's first sub-1-nanometer semiconductor technology, unveiling a new transistor architecture designed to extend chip scaling as AI workloads drive demand for greater compute and energy efficiency. The research device, built around a three-dimensional "NanoStack" architecture, packs nearly 100 billion transistors onto a chip roughly the size of a fingernail. According to IBM, the design could deliver up to 50% higher performance or 70% lower energy consumption than its earlier 2 nm technology.

The announcement centers not on a specific process node but on the architecture behind it. IBM researchers say NanoStack moves beyond today's nanosheet transistor designs by vertically stacking transistor structures through sequential 3D integration. This approach allows additional transistor density while enabling different material combinations within individual stacked layers. "NanoStack is not one innovation," said Huiming Bu, vice president of Silicon Technology Research and Development at IBM Research. "It is actually a device platform" that could support transistor scaling for another decade.

For data center operators, the appeal is straightforward: more compute from the same power budget. As AI clusters push facility power requirements into the hundreds of megawatts, semiconductor advances that improve performance per watt can be as valuable as raw increases in processor performance, enabling operators to expand capacity without matching increases in power and cooling infrastructure.

Research presented at VLSI 2026 demonstrated roughly 40% SRAM scaling using the architecture—a level of memory-density improvement not seen in the industry for over a decade. According to IBM researchers, this additional SRAM density could enable larger caches and other high-speed memory structures used by AI accelerators and high-performance computing systems.

The work also intersects with another major semiconductor trend: backside power delivery. Rather than routing power and signals through the same layers, backside power architectures shift power distribution to the wafer back side, freeing routing resources for signal paths and addressing power-delivery challenges in increasingly dense designs. Technologies such as Intel's PowerVia and TSMC's Super Power Rail reflect the industry's growing focus on power delivery as a scaling challenge. Stacked transistor architectures could make those approaches even more important as device density increases.

While IBM no longer manufactures leading-edge processors, the company's semiconductor research continues to influence the broader industry. "What makes all of this a little different is that IBM is not a manufacturer like Intel, Samsung, or TSMC," said Matt Kimball, vice president and principal analyst for data center technologies at Moor Insights & Strategy. "While IBM performs all of this great research and comes up with amazing breakthroughs, it's usually companies like Intel that bring this research to life through process technology development and manufacturing."

In March, IBM and Lam Research announced a five-year collaboration to develop materials, process technologies and High-NA EUV techniques for sub-1 nm logic scaling, including nanosheet, NanoStack, and backside power delivery technologies. For data center operators, the significance lies less in the node designation than in the potential efficiency gains. "That 1 nm breakthrough is significant precisely because of the power/performance advancements," Kimball said.

IBM researchers said the architecture could help support larger AI accelerators through both improved transistor efficiency and denser SRAM structures. "There are many examples of AI chips that are using more SRAM to scale," said Jay Gambetta, director of IBM Research and IBM Fellow. "Everyone demands more performance, but no one wants to pay the bill for the power," Bu said. "This new innovation will deliver higher performance while reducing power."

However, significant hurdles remain. Moving from a research demonstration to volume manufacturing is challenging, and the semiconductor industry is still ramping up first-generation gate-all-around nanosheet technologies. Sequential 3D transistor stacking introduces additional challenges in thermal management, alignment precision, interlayer isolation and interconnect scaling. "The only pushback is that five years in semiconductors has become potentially five design cycles from the likes of NVIDIA, Intel, AMD and others," Kimball noted.

The industry has also moved away from using nanometer designations as direct measurements of transistor dimensions. Modern process nodes increasingly serve as shorthand for expected performance, power efficiency and transistor density rather than a specific physical feature size. "Focus on performance and power in these node shrinks, and focus more on transistor density to get a feel for how advanced these are," Kimball said. "Using these terms like 2 nm, 1 nm and so on are really the only way we wrap our brains around the performance of a process node generation. Splitting hairs over 1.1 nm versus .9 nm—or .9 nm and .7 nm—is actually pretty close to splitting hairs, literally."

When asked whether NanoStack would affect data center operators within the next decade, IBM executives said they expect the technology to become a mainstream semiconductor technology across the industry. "Within a decade, this will become another mainstream that we have invented and helped industry transform," Bu said.