China's DFSX system claims 2x memory bandwidth vs. Nvidia's GB200 NVL72 using vertical compute-memory tower design at 14nm.

China's Dongfang Suanxin (DFSX) is building a case that memory bandwidth, rather than aggressive node miniaturization, is the key to achieving significant economies of scale for AI workloads. This philosophy is evident in its DF1000 and upcoming DF2000 chips, typically deployed within TY64 SuperNodes to challenge NVIDIA's GB200 NVL72 system.

DFSX's DF1000 chip is fabricated using a mature 14nm process but incorporates a novel 3D near-memory compute architecture. Memory is stacked directly on top of the compute layer and connected via 3D wafer-level hybrid bonding, which fuses the copper pathways of both layers. This approach completely eliminates microbumps and wires, replacing the conventional single horizontal data pathway with millions of ultra-fast vertical connections.

The DF2000 chip, expected to debut in Q4 2026 also on the 14nm node, advances this strategy further. Rather than stacking a single memory layer atop the compute layer, the DF2000 combines multiple stacked memory-compute towers adjacent to one another on a base foundation—a technique DFSX calls the 3.5D Infinity Chiplet layout. The chip replaces basic storage layers with a custom-engineered 3D DRAM layout, dramatically expanding the amount of temporary data that can be stored directly within its structure.

DFSX is targeting a persistent problem in AI workloads: GPU idle time while waiting for data to arrive from memory. The company argues that the memory wall, not node shrinking, represents the primary performance bottleneck.

The numbers support this positioning. Each DF2000 chip delivers 15TB/s of bandwidth. When stacked in a TY64 SuperNode configuration, total memory bandwidth reaches 960TB/s—compared to just 576TB/s for NVIDIA's GB200 NVL72 system, a twofold advantage for DFSX.

The performance gap in compute is more pronounced. The DF2000-based TY64 SuperNode offers 64 PFLOPS of BF16 compute versus 360 PFLOPS for the GB200 NVL72 system. DFSX contends that its superior memory bandwidth will offset raw compute disadvantages in large-scale AI workloads.

Looking ahead, the DF3000 chip is expected to deliver 20TB/s per chip, yielding 1,280TB/s when arrayed in the TY64 SuperNode format. By comparison, NVIDIA's Vera Rubin NVL72 system offers 1,580TB/s of total memory bandwidth—only 23 percent greater than what the DF3000-based TY64 SuperNode will provide. DFSX's core argument remains that FLOPS is an outdated metric for AI workloads; memory throughput is what truly matters at scale.