China's CXMT is pushing ahead with mass production of HBM3E at 20–30% yields, though Samsung-style yield improvements will be difficult to achieve.
China's largest DRAM maker, ChangXin Memory Technologies (CXMT), is moving into production of HBM3E, the fifth generation of high-bandwidth memory (HBM). U.S. export controls have made it harder for Chinese artificial intelligence (AI) chip companies to secure advanced memory, and CXMT is seeking to build a domestic supply chain despite yields of only 20–30% and high production costs. Market observers caution, however, that China will struggle to raise yields quickly. HBM requires not only high-performance DRAM but also an ecosystem that includes stacking and bonding equipment, advanced packaging, and inspection and validation technologies.
**CXMT's Bid to Produce HBM3E**
Reuters reported on the 28th, local time, that CXMT had sent HBM3E samples to several Chinese AI chip designers and planned to begin limited production within the next two months. The company reportedly delivered two versions of HBM3E to customers: a standard design and a modified version with design changes intended to improve yields. CXMT has been developing HBM technology in-house since 2024 and is now making full-fledged preparations to supply the products. However, sources cited by Reuters said its current HBM3E yields are only 20–30%.
The product's performance reportedly is closer to that of the previous-generation HBM3 than to SK hynix's HBM3E. Low yields also drive up unit production costs, so the product is expected to be more expensive than comparable products from overseas competitors. Nevertheless, CXMT is rushing toward mass production because of China's shortage of advanced memory. Since the United States tightened export controls on certain HBM products to China, Chinese companies have been obtaining them through unofficial channels, paying several times their previous prices. Last month, Chinese chipmakers including Huawei and Cambricon raised AI chip prices by 20–50%, citing higher memory procurement costs.
**Samsung Electronics Faces HBM Setbacks**
Market observers say CXMT's situation is reminiscent of the HBM yield problems Samsung Electronics experienced earlier. In 2024, Samsung struggled to achieve sufficient yields and complete quality validation during HBM production. Its HBM3 yields at the time were estimated at 10–20%, far below rival SK hynix's 60–70%. Process limitations associated with Samsung's non-conductive film (NCF) method were cited as a major cause of the decline in production efficiency. NCF involves inserting insulating film between vertically stacked DRAM chips and bonding them using heat and pressure. As the number of layers increases, controlling film thickness and bonding quality becomes more difficult.
A similar controversy arose during quality validation of its next-generation HBM3E products. In May 2024, Reuters, citing multiple sources, reported that Samsung's HBM3 and HBM3E were failing Nvidia's qualification tests because of heat and power consumption issues. In particular, tests conducted in April that year on eight-layer and 12-layer HBM3E products reportedly produced negative results. Samsung denied the report at the time. However, when it announced preliminary third-quarter results in October that year, it acknowledged that commercialization of HBM3E for major customers had been delayed longer than expected. Unable to accelerate the expansion of high-value-added product supplies as memory market conditions improved, Samsung ceded leadership of the HBM market to SK hynix.
**Table 1. Samsung Electronics' HBM Development and Commercialization Process**
| Product | Key Challenges and Changes | Results |
|---|---|---|
| HBM3 | Increasing complexity of the NCF stacking process; difficulty achieving sufficient yields | Lower production efficiency due to yields below those of competitors |
| HBM3E | Heat and power consumption concerns raised; delays in qualification by major customers and commercialization | Delays in expanding HBM supply; weakened market leadership |
| HBM4 | Use of 1c DRAM and a 4nm base die; collaboration between memory and foundry divisions and adoption of DTCO | Stable early mass production; substantial improvements in processing speed and bandwidth |
*Sources: Samsung Electronics, Reuters*
**Overcoming the Crisis Through Ecosystem Capabilities**
The turnaround came during development of the next-generation HBM4. Samsung focused on comprehensively improving product design and production processes by combining its existing DRAM manufacturing technology with its foundry and advanced packaging capabilities. A key change was the use of cutting-edge processes for both the DRAM and the base die, the bottom chip that controls power and signals for the stacked memory chips that make up HBM. Samsung took the initiative in adopting sixth-generation 10nm-class (1c) DRAM for HBM4, while using its own foundry's 4nm process for the base die. It also applied design-technology co-optimization (DTCO), with its memory and foundry divisions collaborating from the design stage, to align the operating characteristics of the two chips and minimize mismatches between manufacturing processes and product design.
These technological improvements translated into better product performance and stable mass production. Announcing mass-production shipments of HBM4 in February this year, Samsung said it had achieved stable yields from the start of production without additional design changes. HBM4's per-pin data rate of 11.7 gigabits per second (Gbps) was approximately 46% above the 8Gbps standard set by the Joint Electron Device Engineering Council (JEDEC), and speeds of up to 13Gbps are achievable. Memory bandwidth per product also increased to as much as 3.3 terabytes per second (TB/s), approximately 2.7 times that of its predecessor, HBM3E.
**Clear Weaknesses in China's Semiconductor Ecosystem**
Samsung's extensive use of its semiconductor manufacturing ecosystem to overcome the crisis reflects the nature of HBM manufacturing. Even when individual DRAM chips perform well, alignment errors or defects during stacking and bonding can reduce finished-product yields. Heat transfer between chips, power delivery, and signal stability must also be managed, which makes close coordination among manufacturing equipment, materials, and design and validation technologies essential. Samsung could draw on its existing DRAM production facilities and related component and equipment supply chains. Its business structure also enabled it to manufacture base dies at its own foundry and integrate them with advanced packaging processes. Cooperation with major global AI chip companies made it easier to incorporate customers' performance requirements from the product development stage.
By contrast, despite rapidly expanding its existing DRAM production capacity, CXMT is seen as lacking capabilities in the equipment and technologies essential to HBM manufacturing. Chinese semiconductor equipment makers including Naura Technology, Maxwell, and U-Precision are developing their own equipment for HBM production in response to U.S. export controls. However, limited mass-production experience and constraints on inspection and testing capabilities appear to be delaying the stabilization of manufacturing processes. One market expert said, "To improve its current yields of just 20–30%, CXMT must refine its HBM3E design while also improving equipment precision, process stability, and inspection and validation capabilities." The expert added, "This will require raising the technological maturity of the entire manufacturing ecosystem by expanding cooperation with materials and equipment suppliers and steadily accumulating mass-production experience."
**EU Also Faces Structural Limitations**
China is not alone in facing these difficulties. The European Union (EU) is also struggling to build industrial competitiveness because of structural limitations in its semiconductor manufacturing ecosystem. In 2023, the EU enacted the European Chips Act and set a goal of mobilizing more than EUR 43 billion (approximately USD 49.5 billion) through public and private investment and other measures to raise its share of the global semiconductor market to 20% by 2030. However, in April last year, the European Court of Auditors (ECA) projected that the EU's share of the global semiconductor value chain would rise only from 9.8% in 2022 to 11.7% in 2030, concluding that the target was effectively out of reach.
An imbalanced ecosystem is cited as a major constraint on the growth of the EU semiconductor industry. Europe is home to ASML, the world's largest lithography equipment maker, the semiconductor research institute imec, and major companies such as Infineon and STMicroelectronics. Yet it remains highly dependent on Asian companies for