Rapidus Japan builds entire return to leading-edge logic on single Hokkaido fab with 2027 deadline and 60 potential customers.
Japan's Rapidus is betting its nation's entire return to leading-edge logic on a single fab in Chitose, Hokkaido, with production targeted for 2027 on a 2nm process that no high-volume customer has yet committed to purchasing.
Since opening the IIM-1 pilot line in April 2025, the company has operated Japan's first mass-production-grade EUV scanner, produced a 2nm gate-all-around prototype that reached expected electrical characteristics in July, and closed a ¥267.6 billion funding round in February that made the Japanese government its largest shareholder. CEO Atsuyoshi Koike stated in February that more than 60 companies are in talks over 2nm capacity, but not one has signed a volume agreement. With its entire production base consisting of the single IIM-1 facility, Rapidus has no diversification and no fallback site if the node does not proceed as planned. Nevertheless, the fab carries the hopes of an entire nation, and its plans are ambitious.
IIM-1, short for Innovative Integration for Manufacturing, broke ground in September 2023 at Bibi in Chitose, with the cleanroom completed in 2024. ASML delivered a TWINSCAN NXE:3800E in December 2024, the first mass-production-grade EUV system installed in Japan, and the tool completed its first exposure on April 1, 2025. The pilot line began operating that month.
Rapidus targets 2027 for mass production, with its business plan pointing to production beginning in the second half of fiscal 2027 and scaling to full volume in 2028. The plan outlines a capacity ramp from roughly 6,000 wafer starts per month initially to around 25,000 within the first year—a fourfold increase the company is counting on to bring per-wafer costs down.
Chitose's location offers abundant water for wafer cleaning, a cool climate that reduces cooling demands, and some of Japan's strongest renewable-energy potential across wind, solar, and hydropower. Local and prefectural authorities have organized around the project under a "Hokkaido Valley" initiative aimed at building a semiconductor cluster spanning Tomakomai, Chitose, and Ishikari.
Rapidus's 2nm node is a gate-all-around nanosheet design derived from the IBM 2nm process announced in 2021, the product of a partnership signed in December 2022. Rapidus engineers worked alongside IBM at the Albany NanoTech Complex in New York to learn the node before transferring it to Chitose. More than 150 Rapidus engineers were dispatched to Albany across 2023 and 2024 to study the node, with roughly 80 later returning to Chitose to transfer and tune the process for production.
The company's differentiator is manufacturing flow. IIM-1 runs single-wafer front-end processing throughout, branded as Rapid and Unified Manufacturing Service, with per-wafer data fed into AI models that Rapidus says will accelerate yield learning and shorten turnaround compared with the batch processing used by TSMC and Samsung. The 2nm Process Design Kit reached early customers in Q1 2026. Rapidus has not published a yield figure, and its public claims extend only to the prototype attaining expected electrical characteristics.
The program extends beyond the wafer. Japan's New Energy and Industrial Technology Development Organization (NEDO) approved fiscal 2026 budget for Rapidus includes funds for chiplet and package design and manufacturing technology for 2nm-generation semiconductors, alongside front-end work. The company has also proposed panel-level glass-substrate packaging as part of its longer-term roadmap. Building back-end capability in Chitose rather than outsourcing would mirror the integrated approach Intel and Samsung take.
Rapidus's February funding round closed at ¥267.6 billion, approximately $1.7 billion, split between ¥100 billion from the government through the Information-technology Promotion Agency and ¥167.6 billion from 32 private companies. The state investment—the first made possible by a 2025 revision to Japan's subsidy law permitting government equity—made Tokyo the largest single shareholder, with a golden share granting veto power over major decisions, including share transfers and technology partnerships.
This round sits atop a much larger commitment from November, when Japan's Ministry of Trade and Industry added approximately ¥1 trillion in support across fiscal 2026 and 2027, lifting total planned government backing to about ¥2.9 trillion. The government added a further ¥150 billion in equity in early June, bringing Rapidus's combined capital and capital reserves to around ¥425 billion. The state's shares are structured as largely non-voting, keeping its formal voting position near 11.5%, but they convert to a controlling stake of roughly 60% if performance deteriorates—a clause that pairs with the golden share to give Tokyo both upside alignment and downside leverage.
Rapidus's buildings and equipment are currently owned by NEDO and leased back, with the company previously obligated to purchase them by fiscal 2027. The government now plans to construct fab buildings and tools with public money across fiscal 2027 and 2028 and transfer them to Rapidus as in-kind contributions in exchange for shares, removing that purchase obligation and converting what had been grant funding into direct ownership.
Koike stated in February that Rapidus was in discussions with more than 60 companies and had issued preliminary price quotations to around 10. Reported names attached to those talks include IBM and Tenstorrent, the Canadian RISC-V accelerator startup. Fujitsu, a founding investor, is separately weighing whether to outsource a 1.4nm CPU for a successor to its Fugaku supercomputer around 2029.
The design partnerships Rapidus has actually signed, however, are with smaller players building energy-efficient AI silicon. Tenstorrent, led by chip architect Jim Keller and currently under consideration for takeover by Qualcomm, agreed in 2023 to co-develop an edge-AI accelerator on the 2nm node under a NEDO and Leading-edge Semiconductor Technology Center project, with Tenstorrent handling the CPU and Rapidus's AI Chip Design Center building the accelerator. Rapidus signed a separate memorandum of cooperation with RISC-V inference designer Esperanto Technologies in May 2024.
Neither amounts to the committed high-volume order Rapidus needs urgently. Koike has described interest as growing "like a runaway steam engine," but interest is not allocation. Rapidus's cost model depends on filling the 25,000-wafer ramp, and a fab running well below capacity carries the same fixed depreciation as a full one. The company has said its homegrown 2nm chips could cost around 10 times more than Japan's current mainstream parts, a premium that will only narrow with volume.
Rapidus represents the leading track of a national plan running on two parallel paths. The other is TSMC's JASM venture in Kumamoto on the southern island of Kyushu, where a first fab backed by Sony, Denso, and Toyota began mass production in December 2024 on mature 12nm, 16nm, 22nm, and 28nm nodes aimed at automotive and industrial chips. A second Kumamoto fab broke ground in 2025, with its planned node upgraded twice—first to 4nm and then to 3nm—with production targeted around 2028. Tokyo is therefore funding mature and specialty capacity through a proven foreign operator in the south while betting on a domestic startup to reach the leading edge in the north.