The 2026 CIOE China exhibition highlights surging demand for optical modules and high-speed interconnects, with Astera Labs components escalating from hundreds to thousands of dollars per unit.

At the 2026 CIOE China Optoelectronics Exposition, crowds were dense. On social media, attendees were offering 2,500 RMB per guided session to secure industry insiders as escorts. Stepping inside the venue made the trend unmistakable: virtually every AI-related segment was heating up. From optical modules and components to high-speed interconnects and data center infrastructure, surging AI demand is lifting the traditionally siloed optical communications supply chain to unprecedented levels of activity.

Astera Labs was also present at this year’s exposition. Founded in 2017, the American semiconductor company initially entered high-speed interconnects with PCIe Retimers and has since expanded its portfolio to cover copper interconnects, optical interconnects, and rack-level connectivity. As of September, its market capitalization had approached $50 billion.

“The higher the compute demand, the faster data exchange between processors must be, and this interconnect ‘nervous system’ must keep pace,” Sanjay Gajendra, President and COO of Astera Labs, told Leifeng Net.

This momentum is driven by the mounting interconnect pressures created by the continuous expansion of AI infrastructure. As GPU counts scale from a handful to dozens, hundreds, or even thousands, the efficiency of data transfer between processors begins to directly dictate the performance of the entire infrastructure stack.

Why did Astera bet on interconnects as early as 2017, well before large language models saw widespread adoption?

“We judged back then that connection architectures designed for previous-generation processors would no longer support system demands when a single server held 10, or today, dozens of processing units,” Gajendra said.

Conventional servers were typically architected around one or two CPUs, with storage and networking treated primarily as peripheral I/O. However, as CPUs, GPUs, SmartNICs, and other processors increasingly operate concurrently within a single chassis, the volume of data requiring internal exchange has risen sharply.

“It’s like having many ‘brains’ in one machine; interconnect architectures originally designed for a small number of processors can no longer sustain their data exchange,” Gajendra explained.

By 2026, this challenge has intensified alongside AI’s rapid evolution. Gajendra summarizes the current interconnect architecture’s hurdles through three variables: speed, scale, and power consumption. Around the time Astera was founded, PCIe single-lane rates hovered around 8 GT/s; today, they have reached 64 GT/s. AI systems have similarly scaled from early configurations of four to eight GPUs to deployments spanning dozens, hundreds, and beyond.

“To keep pace with current AI deployments, data transmission speeds are doubling every year,” Gajendra noted. Alongside scale expansion, communication latency must be minimized while maintaining memory consistency and processor synchronization. As system footprints grow, the power consumption of the interconnect itself has emerged as a hard constraint.

This expansion pressure is actively reshaping the copper-to-optical boundary, breaking the conventional assumption that copper dominates short distances while optical takes over long ones. Distance is no longer the primary determinant for choosing between the two. Instead, Gajendra identifies transmission rate and GPU scale as the two core variables dictating when rack-level architectures should transition from copper to optical.

For connections operating at 200G per lane, copper interconnects remain fully capable. Beyond 400G per lane, however, optical solutions will increasingly penetrate rack interiors. The rising connection density and thermal management pressures driven by larger GPU counts will further influence customer decisions between copper and optical interconnects.

Complicating the copper-optical calculus is cost. Every vendor ultimately must run the numbers: what is the total system token cost associated with each connection methodology?

During the exposition, an Astera Labs engineer told Leifeng Net that copper and optical will not simply replace one another in next-generation AI systems. A vast majority of short-distance links will continue to favor copper due to its lower cost and technological maturity. Yet, as systems scale to thousands of GPUs across multiple racks, the decisive metric shifts to the unit token cost of the entire infrastructure.

The engineer added that, using Nvidia’s NVL72 platform—featuring a 72-GPU scale-up domain—as a benchmark, expanding compute requirements will push organizations toward larger scale-up domains. This reduces the frequency with which data traverses scale-out networks, which typically route through NICs, Ethernet, or InfiniBand switches, introducing additional latency and architectural complexity. By leveraging optical interconnects to expand scale-up boundaries, companies can further optimize the unit token cost of their systems.

On the technology roadmap, Gajendra anticipates that Near-Packaged Optics (NPO) will begin entering scale-up deployments around 2027. Co-Packaged Optics (CPO), while already seeing limited applications, is unlikely to achieve large-scale deployment within scale-up domains until after 2029 or 2030.

Viewed through this lens, the central question for AI interconnects is no longer merely “how to transmit data faster,” but rather how to organize increasingly numerous GPUs through diverse connection methodologies while driving down the cost per token.

Capital expenditures are stabilizing, but value capture continues to rise.

Over the past two years, the most direct growth driver for AI infrastructure has been the sustained capital expenditure increases by hyperscale cloud providers. Clearly, such spending cannot maintain identical growth rates indefinitely. When asked whether a potential slowdown in AI data center construction by leading cloud vendors over the next one to two years would impact interconnect suppliers like Astera Labs, Gajendra did not rule out the possibility.

He acknowledged that AI remains in a concentrated infrastructure build-out phase, with U.S. hyperscalers alone having publicly committed to over $1 trillion in data center investments. However, as large-scale construction phases conclude, capital expenditures will inevitably stabilize over the coming years.

Investors are growing increasingly sensitive to how long this spending trajectory can hold. According to public disclosures, Microsoft, Alphabet, Amazon, Meta, and Oracle are projected to spend approximately $795 billion collectively in 2026, rising to nearly $1.08 trillion in 2027. The market is closely monitoring these figures for any signs of deceleration.

For Astera, the strategic response is not to wait passively for cloud providers to build more facilities, but to increase the value captured per accelerator. Gajendra provided a clear progression: in the early days with only the Aries PCIe Retimer, Astera’s product value per accelerator was under $100. After integrating switch chips and memory products, that figure climbed into the hundreds. With the advent of scale-up switching, the value per accelerator has now reached the thousands.

Scale-up is clearly the direction Astera is doubling down on. Gajendra revealed that the company originally expected its Scorpio series to become its largest revenue-generating product line in the fourth quarter of this year, but that milestone has been accelerated to the third quarter.

Beyond increasing per-accelerator value, Gajendra points to the inference market as another critical growth vector.

While both training and inference demand high bandwidth, low latency, and low power from interconnects, their workload priorities diverge. Training leans heavily on raw compute throughput, whereas inference places greater emphasis on memory access patterns and ultra-low latency.

Unlike training, which remains concentrated in massive data centers, Gajendra notes that the inference landscape will feature more fragmented participants and varied system architectures. “Especially in inference, more customers will enter. It’s a highly fragmented market with many players and many system configurations,” he said.

Future interconnect demand will not hinge solely on how many massive training clusters a handful of top cloud vendors build. As AI workloads pivot toward large-scale inference, connectivity requirements will extend across a wider spectrum of system sizes and deployment models.

As customer profiles and deployment formats multiply, interconnect vendors will no longer face a monolithic set of requirements. Different markets and customer segments are increasingly diverging in their expectations regarding standardization, product iteration velocity, and system customization.

These distinctions are particularly pronounced between the U.S. and Chinese AI infrastructure markets.

As the inference market fragments, interconnect suppliers encounter an ever-more diverse customer base. Compared to North America, China’s AI infrastructure ecosystem exhibits a distinctly different client composition.

Gajendra noted that the North American market is currently dominated by four hyperscale cloud providers—Amazon, Microsoft, Google, and Meta—alongside major AI research labs like OpenAI and Anthropic. In China, in addition to internet giants like ByteDance and Alibaba, a vast array of startups of varying sizes are actively participating in AI infrastructure development.

“If summarizing a difference, opportunities in the Chinese market advance very quickly,” Gajendra said. With more participants and broader application scenarios, Chinese clients demand faster vendor responsiveness and quicker product deployment cycles than their North American counterparts.

An Astera engineer also highlighted that large U.S. customers typically prioritize standardization, supply chain reuse, and cross-generational product compatibility. In contrast, Chinese clients are more willing to experiment with alternative technical approaches and place a higher premium on rapid commercialization.

Although internal customer systems will grow increasingly customized, external connection interfaces will remain standardized. “Customization will increase and continue, but everyone will still strive to adopt open standards. External connections and interfaces will stay standardized, while internal processor architectures will be customized based on different workloads and performance metrics,” Gajendra stated.

He cited ByteDance and Alibaba as examples: ByteDance’s infrastructure primarily serves its own internal operations, whereas Alibaba must support both internal applications and external cloud services. Consequently, their processor and server designs will inherently differ.

As AI systems become more internally customized, the interfaces connecting those systems require even stricter standardization. For interconnect vendors, the task is no longer adapting to a single, unified server architecture, but rather accommodating an expanding matrix of processors, workloads, and deployment configurations.

From copper-to-optical trade-offs and scale-up expansions to the divergent customization and standardization demands of different clients, interconnects are transitioning from a peripheral supporting component to a foundational element of AI infrastructure design.

When connection methodologies simultaneously dictate GPU scalability, system latency, and token economics, their value transcends mere data transport. They ultimately determine whether raw compute capacity can be effectively converted into usable system performance.