Intel touts its U.S. advanced packaging capabilities for next-generation AI semiconductors, positioning itself as a geopolitically-backed domestic alternative to TSMC.

As AI demands unprecedented computing power, the semiconductor industry has moved beyond single, massive chips. Advanced packaging—the craft of interconnecting multiple specialized chips—enables them to function as a unified, powerful system capable of handling massive workloads at unprecedented speeds.

Intel has been pioneering advanced chip packaging for years both domestically and globally. It remains one of the most critical components in creating multi-chip packages for today's technology products.

**U.S. Advanced Packaging: Intel's Rio Rancho Facilities**

At Intel's Rio Rancho, New Mexico facilities, advanced packaging technologies are expanding the "reticle limit"—scaling packages to 8 times the industry standard today, and over 12 times by 2028. The operation has evolved from the era of single large chips to what Intel describes as a "silicon mosaic," where specialized tiles are interconnected within a single, massive package.

"Back in the 1980s this site was the leader in 6-inch wafer manufacturing. Now over 40 years later, things have flipped and this site is the leader in the United States for advanced packaging," explains Katie Prouty, manager of Intel's Fab 9 advanced packaging facility.

To meet AI's massive demands, Intel is pushing physical boundaries through Foveros stacking and EMIB interconnects. "Some of the customers are coming to us first for advanced packaging," Prouty notes. "When we're successful delivering to those customers, they'll continue to grow their trust and faith in Intel as a foundry."

The Rio Rancho site has grown from 25 employees in 1980 to 2,700 employees today, supported by 500 suppliers delivering critical U.S. advanced packaging technology to market.

**Foveros: Intel's Advanced Packaging Process**

One key process at Fab 9 connects smaller specialized chip tiles—chiplets—into a single, high-performance system using Foveros technology, which attaches these chiplets to a silicon interposer, analogous to a pizza crust.

"Inside the fab, the chip attach tool is the first step in Intel's Foveros advanced packaging process," explains Chris Seibert, Principal Engineer at Fab 9. "If we use a food analogy, this is the tool that brings in a 'pizza crust,' or silicon wafer, and whatever 'pizza toppings' or specialized chiplets you want, we feed into the other side of this machine, and it attaches them to the top of that crust."

The wafer then travels to a bake-like tool that fuses the system together. Once complete, an overhead robot track system called FOUPs (front-opening unified pods) transports the wafer to another machine where epoxy fills beneath and around the "pizza toppings," securing everything in place.

Finally, water-cooled blades dice the wafers into individual packages with precision. "The great part about that process is it lets us take a bunch of different chips from different designs or different technology nodes and put them all together onto one wafer," Seibert says.

Using Foveros, individual chiplets function as a single powerful unit that runs faster while handling massive workloads. The technology extends battery life by placing power-hungry circuits on more efficient process nodes, allows laptops to become thinner, and enables edge computing devices to fit into smaller spaces without sacrificing performance. More features can be packed into smaller footprints, from the factory floor to the desktop.

**EMIB: Embedded Multi-Die Interconnect Bridge Technology**

EMIB (Embedded Multi-Die Interconnect Bridge) is another critical advanced packaging technology, where specialized chips are linked together on a package with tiny silicon bridges. This approach enables different chips to function as a single unit, delivering the massive power needed for AI while improving efficiency and reducing manufacturing costs.

Unlike other foundries that use expensive silicon interposers as connection layers between chips, Intel embeds tiny, high-speed silicon bridges only where needed—a data shortcut that slashes costs and transforms the "silicon mosaic" of chiplets into an AI powerhouse. When large data center chips sit adjacent, EMIB creates a bridge directly underneath so they can communicate efficiently.

**EMIB-T: The Latest Development**

In 2026, EMIB-T represents the latest advancement, adding channels through the bridge to deliver power directly to chips rather than routing around them. This improves power efficiency and signal routing required by the latest high-bandwidth memory (HBM) technologies.

Only Intel Foundry can mix and match chiplets from different sources directly onto the industry's largest substrates, providing the flexibility needed to build the massive, side-by-side AI engines that power today's data centers.