Taiwan Semiconductor's first batch of CoPoS demonstration tools entered the validation phase this month. Driven by industry reports and research notes, the company's stock price hit multiple highs in June, closing at a new record yesterday.

The CoPoS concept has triggered volatility in upstream sectors, including glass substrates, packaging and testing (OSAT), and semiconductor equipment, bringing a valuation premium to the next-generation technology branch in advanced packaging. Companies such as Teradyne, ASE Technology, Corning, and MKS Inc in the inspection components sector all closed at record highs yesterday.

Notably, TSMC's management stated that CoPoS will not replace CoWoS in the short term. On the contrary, CoWoS capacity will continue to expand rapidly over the next few years.

**What is CoPoS?**

CoPoS stands for Chip-on-Panel-on-Substrate, representing TSMC's next-generation ultra-large-size advanced packaging for AI chips. It features two key characteristics.

First, square panels replace circular silicon wafers, significantly increasing the upper limit of packaging area. Twelve-inch circular wafers suffer from severe edge waste, with a chip area utilization rate of only 65%-70%. In contrast, square panels can achieve a utilization rate of 80%-90% or higher. A 510×515mm panel offers an effective area 4.5 times that of a 12-inch wafer, drastically boosting output per batch.

Second, a glass core substrate paired with ABF build-up layers replaces the traditional silicon interposer, reducing packaging costs by 20%-30%, minimizing warpage, and delivering higher bandwidth.

**Which Companies Will Benefit?**

As the core beneficiary of CoPoS, Taiwan Semiconductor offers the highest earnings elasticity. The trading logic is that while CoWoS capacity is tight in the short term, CoPoS will secure TSMC's monopoly in next-generation ultra-large AI chip packaging in the medium to long term, extending its packaging advantages well beyond 2030.

Intel's market performance is not directly tied to CoPoS. The bullish logic stems from its proprietary EMIB packaging absorbing overflow orders from TSMC's CoWoS capacity constraints, representing a competing technology route. Amkor Technology and ASE Technology and other OSATs are rising in tandem with the sector. The market is speculating on the expected volume of outsourced CoPoS supporting orders. ASE handles some of TSMC's backend packaging processes, riding the sector's momentum. However, core processes and high-margin segments remain within TSMC's in-house production lines.

Market expectations suggest that NVIDIA's next-generation Feynman GPU will adopt the CoPoS solution, serving as a validation target for industry demand.

Glass substrate manufacturers are gaining incremental valuation premiums. Key players in this field include Absolics, a glass substrate subsidiary of SK Group affiliated with SKC, and Corning, which has R&D and production layouts in Glass Core Substrates and Through Glass Via technology, making it a major supplier in this space.

Applied Materials provides thin-film deposition equipment, which is core to the RDL (Redistribution Layer) process. The RDL is a thin metal wiring film used in advanced semiconductor packaging. Because chips have tiny, tightly packed connection points that cannot link directly to substrates, the RDL redraws these microscopic pins into wider, neatly arranged metal lines. It builds multi-layer circuits to connect GPUs, HBM memory, and small chiplets, enabling fast data transfer between different chips.

KLA Corp's products address panel warpage and large-size packaging defect inspection. This is a strict necessity for yield management and carries extremely high entry barriers.

Lam Research provides core equipment for dry etching and TGV (glass via) etching.

MKS Inc and Screen Holdings supply high-performance electroplating machines for ultra-fine RDL lines on wafers and large glass panels, as well as laser ablation systems for glass TGV and chiplet surface treatment.

Disco supplies critical wafer and glass substrate processing machines for CoWoS and CoPoS packaging. Its laser dicing and cutting systems separate chiplets, HBM stacks, and large glass panels without cracking fragile wafers.

**Risk Warnings**

CoPoS is only undergoing pilot line validation in June. Pilot production is scheduled for 2027, with mass production in 2028. It will take more than two years before actual earnings materialize. Capital is currently focusing on bottom-fishing, lacking short-term earnings catalysts. Compared to the immediate capacity shortages in HBM and CoWoS, CoPoS represents a long-term industry alpha thesis. Its price action is wave-like, driven by pulses in research reports and industry news.

Capital will not hype the CoPoS concept in isolation; it is always bound to the broader logic of long-term bottlenecks in AI chip packaging. If the sector pulls back, the valuation premium may shrink.