Positron AI, 고가 HBM 대신 범용 DRAM을 사용하는 추론 칩 상용화를 위해 8억 7500만 달러 펀딩 확보

A Reno-based AI hardware startup has just made the most explicitly engineered argument against Nvidia's memory architecture in the inference era: that the problem isn't how much bandwidth an accelerator can peak, it's how much of that bandwidth gets used — and that commodity memory, purpose-built for inference decode, can match what High Bandwidth Memory delivers in practice even if it can't match it on a spec sheet.

Positron AI announced Wednesday the close of an $875 million Series C financing round at a $5 billion post-money valuation — a roughly fivefold increase from the $1 billion-plus valuation the company held after its $230 million Series B in February 2026. The round came two days after Qualcomm and Amazon disclosed a multi-generational LPDDR-based inference partnership worth up to $60 billion in purchases — a deal that independently validated the architectural thesis Positron is betting on.

The funding will support the tapeout of Asimov, Positron's custom inference ASIC on TSMC N3P, targeted for late 2026, with production scheduled for the second half of 2027. Asimov's defining characteristic is that it uses LPDDR5X — the same commodity DRAM class found in smartphones and laptops — rather than High Bandwidth Memory, the 3D-stacked specialty memory that powers Nvidia's H100, H200, and Rubin-series accelerators.

## Inference Spending Just Passed Training — and Memory Is the Fight

The timing matters. In August 2026, Gartner reported that inference surpassed training spending for the first time this year, with global AI inference at $23.3 billion versus $19 billion for training — a structural inflection point the research firm attributed to the shift from model development into continuous, real-time deployment. AI-optimized infrastructure spending broadly is growing 96 percent year over year to $42.3 billion. The era where AI infrastructure meant "where do I train my model" is over; it now means "how do I serve it continuously at scale."

That question runs directly into a supply-chain problem. High Bandwidth Memory, the stacked DRAM technology that delivers the terabytes-per-second bandwidth Nvidia's GPUs are built around, is produced by a narrow set of suppliers and packaged through an advanced process called CoWoS (Chip on Wafer on Substrate), which only a handful of fabs worldwide can perform. HBM demand is growing at roughly 60 percent per year, and capacity cannot keep pace. The consequence reached Nvidia's own roadmap: as Positron investor Forest Baskett of NEA noted in the round announcement, the Rubin Ultra GPU reportedly scaled back from a terabyte of HBM4E memory to approximately 192GB because the supply simply wasn't available.

## Why Bandwidth Utilization Beats Raw Bandwidth — and Why That Claim Is Still Unverified

Positron's core argument is that the comparison between HBM and LPDDR5X based on peak bandwidth numbers misses how AI inference actually works.

Modern large language model inference runs in two phases: prefill, where the model processes an input prompt in parallel using heavy matrix computation, and decode, where it generates output tokens sequentially, one at a time, reading from a stored key-value (KV) cache with each step. Prefill is compute-bound and saturates GPU tensor cores. Decode is memory-bound — it reads the entire KV cache for every generated token, but it does so sequentially rather than in parallel, which means the bottleneck is how efficiently the hardware moves the data it already has, not how fast it can theoretically move data in a best-case scenario.

This is the gap Positron is exploiting. GPU inference deployments — designed originally around training workloads that demand massive parallel bandwidth — typically achieve less than 30 percent of their available memory bandwidth during inference decode, according to Positron's own claims. Positron says its memory-first architecture achieves over 90 percent. If those figures hold across production workloads, the effective bandwidth delivered to the model is comparable even when the raw peak numbers are not.

That is a significant architectural claim. It is also currently company-stated and unverified by independent third parties. Tom's Hardware noted in July 2025 that Positron's Atlas performance comparisons against Nvidia's H200 DGX "require verification by a third party." More directly, The Register's analysis earlier this year calculated that Asimov's design target of approximately 2.76 terabytes per second of realizable bandwidth compares to roughly 22 terabytes per second of peak HBM bandwidth in Nvidia's Rubin accelerator. Even at 30 percent GPU utilization, Rubin's memory system would be roughly 2.4 times faster. Positron's counterargument — that inference workloads don't approach that utilization level on GPU hardware — has not been confirmed through published third-party measurement of Asimov, which has not yet taped out. Every Asimov performance figure is a design target, not a silicon result.

## Inside the Architecture: What LPDDR5X Makes Possible

The practical case for LPDDR5X beyond the utilization argument comes down to supply chain and scale.

Positron's Asimov chip uses an organic substrate rather than the silicon interposer required by CoWoS packaging — which is what makes HBM possible and also what makes it scarce. LPDDR5X is produced at commodity scale by multiple suppliers including SK Hynix, Samsung, and Micron; it requires no specialized advanced packaging; and its per-gigabyte cost is substantially lower than HBM. Asimov is designed to carry between 288 gigabytes and 2,304 gigabytes of memory per chip, with the upper end achievable through CXL (Compute Express Link) expansion — a memory pooling protocol that lets the chip access additional memory capacity beyond what is physically on the package. Titan, the system built around four to eight Asimov chips, is designed to serve models exceeding 16 trillion parameters with context windows beyond 10 million tokens in a single node.

For context: Nvidia's H100 ships with 80 gigabytes of HBM3; the H200 ships with 141 gigabytes of HBM3e; the upcoming Rubin architecture targets 288 gigabytes of HBM4 — a figure that now appears to have been scaled back from the originally announced one terabyte due to supply constraints. Asimov's lower end (288 gigabytes) matches Rubin's reduced HBM4 target; its expandable upper end (2.3 terabytes) has no direct equivalent among current GPU configurations.

Titan is also designed to operate in both air-cooled and liquid-cooled data centers at varying rack densities. This is not a minor convenience feature: many enterprise facilities cannot accommodate the thermal and power provisioning requirements of dense liquid-cooled GPU clusters, which means Positron can address infrastructure that Nvidia's highest-density configurations structurally cannot reach.

## Atlas Is Shipping — and the Oracle Deployment Is the Proof of Concept

Positron isn't pitching future silicon alone. Its first-generation Atlas inference system is already deployed at Oracle Cloud Infrastructure in more than 50 racks, with the inference service Parasail drawing on that capacity for its own customers. Jump Trading and i3d.net are also confirmed Atlas production customers.

Cloudflare tested Atlas hardware in 2025, and reporting from Tom's Hardware documented that the system claimed 280 tokens per second per user on the Llama 3.1 8B benchmark in a 2,000-watt power envelope, compared to roughly 180 tokens per second per user for an eight-way Nvidia DGX H200 server. That comparison requires third-party verification, as Tom's Hardware noted, and it covers Atlas rather than Asimov — the current shipping product, not the custom ASIC targeted for 2027.

CEO Mitesh Agrawal described the Oracle deployment as the primary engineering input for Asimov: "Deploying Atlas at scale taught us an enormous amount about what inference customers actually need, and we have carried those lessons directly into Asimov and Titan."

## The Round: Who Is Betting and Why It Signals More Than Money

The financing came in two tranches. The first, a $375 million Series C at a $3.5 billion pre-money valuation, was co-led by NEA, Andra Capital, Atreides Management, Valor Equity Partners, and Dylan Patel's SemiAnalysis Capital. The second, a Series C-1 of up to $500 million, was led by NEA and Jim Clark — the engineer who founded Silicon Graphics in 1982 and co-founded Netscape in 1994 to commercialize the web browser. Additional investors include DFJ Growth, the Qatar Investment Authority, Resilience Reserve, Cisco Investments, Hudson River Trading, Naver Ventures, and Liberty Global Tech Ventures.

Clark's involvement carries a specific pattern-recognition resonance: Silicon Graphics built its business around purpose-built silicon for a specialized computational workload (3D rendering) at a moment when general-purpose hardware could not efficiently serve that workload — exactly the architectural thesis Positron is pursuing in inference.