AI tools including OpenAI's Jalapeño and traditional EDA software are being deployed in modern semiconductor design workflows to accelerate chip development.

In late August, Architect Labs announced that it had designed a chip almost entirely by AI—claimed as an industry first. AI is already deployed across multiple stages of semiconductor development: optimizing floorplans, placement and routing, and verification. Generative AI can assist engineers with RTL code, while emerging agentic systems can operate electronic design automation (EDA) tools, analyze results, identify problems, modify designs, and iterate with progressively less human intervention. Yet human engineers still define architectures and make fundamental design decisions that determine what a chip does and how it operates.

This creates an interesting feedback loop. Today's AI models run on processors designed by human engineers with growing AI assistance; those models can then help design more capable processors for the next generation of AI systems. As EDA vendors and semiconductor companies grant AI control over larger portions of the design process, the industry is gradually transitioning from humans using AI tools to design chips toward AI systems participating in the design of the hardware on which their successors will run.

Can machines truly design machines today? Probably not. But will they be able to in the future? That question carries important ramifications—and engineers have been contemplating it longer than many realize.

**A brief history of AI in chip development**

Cadence, Synopsys, and Siemens EDA, alongside Ansys, all leading developers of EDA and simulation software, released AI-enhanced versions of their tools in the early 2020s, before generative AI transformed the industry.

The first generation of AI-enhanced EDA software primarily used machine learning and reinforcement learning to solve well-defined optimization problems. Given an existing design, constraints, and specific targets, these tools could explore numerous implementation options to optimize placement and routing—and therefore power, performance, and area (PPA)—while reducing development time. AI could find better ways to implement a design, but the design itself and its goals remained the domain of engineers.

A key advantage was the ability to learn from previous runs and use accumulated data to guide subsequent design-space exploration, reducing iterations needed to meet PPA targets and sometimes producing results that would have required substantially more engineering effort with conventional methods. However, autonomy was limited: engineers defined constraints, configured flows, ran individual tools, analyzed output, and decided what to try next. AI accelerated or optimized particular development stages, but humans controlled the overall design flow. That is changing with newer generations.

The latest AI-enhanced EDA tools are considerably more ambitious. Generative AI can write or modify RTL and verification code, analyze reports, identify potential failure points, and suggest fixes. Emerging agentic systems can operate multiple EDA tools and execute sequences of engineering tasks with minimal human intervention, analyzing results, modifying designs or parameters, launching new simulation runs, evaluating outcomes, and repeating until specified targets are reached. AI is thus moving from optimizing individual steps within EDA tools to automating portions of the entire chip development workflow.

**From big bang to architectures**

In 2023–2024, both Cadence and Synopsys announced that hundreds of chip designs had been completed using their AI-enhanced tools (Cadence.ai DSO.ai/VSO.ai/TSO.ai). Leading high-tech companies disclosed details about their AI-driven projects. Yet grouping Google, Nvidia, OpenAI, and Architect Labs together misses important distinctions—they represent different degrees of AI involvement in chip development.

Google, among the first major technology companies to announce AI-driven development of AI accelerators, appears to be the least radical in its approach. Google's AlphaChip uses reinforcement learning primarily for physical floorplanning: it places circuit blocks and optimizes layouts, but does not invent the entire design or architecture. Google DeepMind reported in 2024 that AlphaChip had been applied to the previous three generations of TPUs, placing Google ahead of the general EDA industry. (The company has not shared detailed progress since then.)

Nvidia's approach is more notable because its internal AI systems automate work traditionally performed by hardware engineers. The distinction lies in Nvidia's ability to train specialized models on its own RTL, documentation, and proprietary accumulated engineering knowledge—something merchant EDA vendors cannot access. This exemplifies a chip designer converting the engineering data behind its proprietary GPUs, AI accelerators, CPUs, DPUs, and network cards into training data for AI. Yet Nvidia itself maintains a clear boundary between its automation and autonomous chip design.

OpenAI's Jalapeño represents probably the strongest real-silicon example to date. OpenAI says AI was directly involved in implementation, design-space exploration, verification loops, and arithmetic-circuit optimization, enabling the company to progress from initial design to tapeout in nine months. At Hot Chips, OpenAI disclosed concrete performance metrics: compared with human baselines, AI-assisted designs improved a BF16 multiplier by 56%, an FP4 dot-product block by 21%, and an FP32 accumulator by 10%, while reducing the area of matrix and SIMD units by 10% and 8% respectively.

OpenAI has not claimed that AI invented Jalapeño's architecture, so humans remain responsible for it. But AI was extensively applied to turn that architecture into silicon and optimize it—which brings us to Architect Labs.

Architect Labs' Redwood is qualitatively different. Two human architects defined the specification; after that, Architect Labs states its AI autonomously generated and verified the logic, generated RTL, verified it, and produced firmware. AI also assisted software development, including drivers and kernels. Unlike Google, Nvidia, and OpenAI, the company explicitly describes its system as performing machine learning co-design and says it can explore architectures, though without elaboration.

Redwood was produced in under two weeks and runs billion-plus-parameter models, but a significant caveat applies: it has not been taped out. It has never been produced as an ASIC; the accelerator runs on an FPGA, and the claimed 3.4X performance-per-watt advantage over Nvidia's Jetson Orin Nano is based on a projected Samsung 8LPP design.

**Final words**

Just years ago, AI in semiconductor development was largely an optimization technology that helped engineers find better ways to implement human-designed chips. Today, it can generate RTL, verify designs, operate EDA tools, and even explore architectural choices—though humans still define what ultimately gets built.

We are considerably closer to machines designing machines, but nowhere near true autonomy. For now, chips are helping design their successors. But they remain far from deciding what those successors should be.