SK Hynix is advancing co-packaged optics (CPO) as a strategic complement to its HBM roadmap to meet future AI interconnect demands.

AI chips are rapidly increasing in computational power, but inter-chip data movement has emerged as a critical bottleneck. To address this, the industry is advancing Co-Packaged Optics (CPO), a technology that utilizes light to accelerate data transfer. SK Hynix is now positioning itself to enter the CPO market, aiming to integrate CPO with its High Bandwidth Memory (HBM) and memory-pooling technologies to enhance overall AI system performance. However, realizing this strategy will require leveraging key technologies from TSMC. Specifically, TSMC’s COUPE architecture connects electronic and optical chips, its System-on-Integrated-Chips (SoIC) enables vertical chip stacking, and its Chip-on-Wafer-on-Substrate (CoWoS) platform facilitates the integration of processors, HBM, and optical components into a single package. Beyond semiconductor fabrication, CPO development demands expertise in optical fibers, micro-lenses, precision alignment, packaging, and testing—creating significant opportunities for Taiwanese supply chain partners. Sung-Chuan manufactures Fiber Optic Array Units that interface optical fibers with silicon photonics chips, currently developing solutions targeting 1.6T, 3.2T, and ultimately 6.4T speeds. Largan Precision is engineering compact optical components and fiber arrays for CPO applications, with mass production potentially commencing as early as 2027. Meanwhile, Xunxin-KY is focusing on CPO packaging; its 51.2T product has entered small-scale production, while a 102.4T variant is currently undergoing testing. Ultimately, SK Hynix’s CPO ambitions will rely heavily on TSMC and specialized Taiwanese firms to deliver the necessary foundational technologies.

These developments unfold against a backdrop of intensifying competition and strategic realignment across the semiconductor sector. Samsung and SK Hynix are simultaneously ramping up chip production and upgrading semiconductor laboratories to improve yields, responding to surging AI-driven demand. According to Bank of America, both companies are projected to benefit from the ongoing memory boom through 2027. However, their dominance in long-term supply agreements is no longer exclusive, as competitors increasingly secure multi-year contracts. In parallel, SK Hynix continues to expand its production network with new fabrication plants to safeguard future AI growth, even as executives from both Samsung and SK Hynix navigate ongoing police investigations.

Complicating the competitive landscape is a high-stakes intellectual property dispute between Samsung and China’s ChangXin Memory Technologies (CXMT). Following fresh testimony in South Korea, a former Samsung engineer who defected to CXMT reportedly stated that the Chinese memory manufacturer actively sought Samsung’s proprietary process know-how during its formative years. Prosecutors allege that Samsung’s 18-nanometer DRAM technology was acquired and subsequently adapted for CXMT’s manufacturing operations. The contested intellectual property encompasses Samsung’s Process Recipe Plan—a highly granular set of manufacturing instructions spanning hundreds of production steps. Should Korean courts accept this testimony alongside other evidence, Samsung may leverage the findings to initiate legal proceedings against CXMT. A primary avenue for recourse is the U.S. International Trade Commission (ITC), which possesses the authority to restrict imports under Section 337 rulings. Historically, Samsung’s litigation against Chinese display manufacturer BOE resulted in a recommended 14-year-and-eight-month exclusion order before the broader conflict was resolved via settlement. For a potential U.S. ban to materialize, Samsung must still establish a direct legal nexus between the alleged trade-secret misappropriation and imported goods. While a prohibition remains a possibility rather than a certainty, any successful outcome would significantly impede CXMT’s ambitions to penetrate the global DRAM market, particularly within the United States.

Simultaneously, the custom AI accelerator market is experiencing heightened fragmentation. AMD is reportedly entering the bespoke AI chip space, with Google positioned as a potential inaugural major client. Reports indicate Google is collaborating with AMD to develop one of its next-generation Tensor Processing Units (TPUs), which underpin Google’s AI computing infrastructure. While Broadcom has served as Google’s primary TPU supplier for years, the tech giant is actively diversifying its supply base. MediaTek is also believed to have secured preliminary TPU orders, though the company has not officially confirmed the arrangement. AMD’s involvement is expected to intensify market competition, leveraging its extensive processor and chip design expertise to potentially co-locate CPUs and AI accelerators, thereby enhancing system speed and efficiency. Neither Google nor AMD has formally validated the partnership, but its realization would mark a pivotal expansion for AMD’s business portfolio. Broadcom remains a critical ally, concurrently collaborating with Google and AI firm Anthropic on next-generation computing architectures. MediaTek is similarly scaling its AI hardware division, recently announcing the development of an AI accelerator for a major U.S. cloud provider, with mass production slated for imminent rollout. This competitive shift aligns with Google’s broader capital strategy: the company plans to allocate $175 billion to $185 billion toward infrastructure investments in 2026, with a substantial portion directed at AI and cloud computing. The reported AMD engagement underscores a rapidly maturing ecosystem where AMD, Broadcom, and MediaTek are vying for dominant positions in Google’s procurement pipeline.

On the manufacturing front, Samsung is accelerating its advanced foundry footprint in Texas, with preparations for the second Taylor semiconductor facility already advancing ahead of schedule. Industry sources indicate Samsung has instructed key equipment vendors to initiate certification processes for machinery installation at the upcoming site. This proactive step precedes the company’s planned groundbreaking later this year and suggests operational planning is proceeding despite final equipment and production specifications remaining partially undetermined. During its second-quarter earnings call, Samsung confirmed it intends to break ground on Taylor Fab 2 by the end of 2026, targeting mass production commencement in 2030. Executives cited escalating customer demand for advanced foundry capacity as the primary catalyst. The Taylor campus is engineered to serve as a cornerstone U.S. manufacturing hub for Samsung’s leading-edge logic chips, encompassing multiple fabrication plants and R&D divisions dedicated to advanced process nodes, including 2nm production. Concurrently, the initial Taylor fab is nearing operational readiness, with equipment installation and production trials actively underway. Tesla is anticipated to become a flagship customer following a $16.5 billion chip manufacturing pact with Samsung. Consequently, Taylor Fab 2 will serve as a critical stress test for Samsung’s ability to translate foundry interest into sustained volume production. Samsung has previously noted that customer commitments will dictate the pace of capacity expansion, particularly as industry attention shifts toward future nodes like 1.4nm. With equipment suppliers already mobilizing for certification, Samsung is effectively pre-positioning its infrastructure ahead of physical construction.

Central to this expansion is Samsung’s strategic push to secure Tesla’s next-generation AI5 and AI6 chips, which will be manufactured using Samsung’s advanced 2nm process. Large-scale production is projected to commence in 2027, with the agreement valued at approximately 20 trillion won. Beyond its financial magnitude, the partnership carries profound strategic weight for Samsung. Successfully delivering these chips would validate the yield capability and quality consistency of its 2nm technology at commercial scale. Given that Tesla’s silicon will power autonomous driving systems and onboard AI workloads, extreme reliability is non-negotiable; any critical failure poses severe safety implications, making Tesla a rigorous benchmark for Samsung’s manufacturing maturity. The deal is particularly vital for the Taylor facility, which has absorbed over $37 billion in capital expenditure. Sustained high-volume orders are essential to optimize line utilization, amortize fixed costs, and drive continuous process refinement. The anticipated 2nm volume from 2027 would directly support these objectives while reinforcing the economic viability of Taylor Fab’s Phase 2 expansion by 2030. Ultimately, securing Tesla’s production could substantially elevate Samsung’s foundry reputation, maximize Taylor Fab’s throughput, and strengthen its competitive posture against industry leader TSMC.

Against this backdrop of aggressive capacity building and architectural innovation, TSMC continues to advance its technological roadmap. The foundry giant has recently unveiled A16, a new process technology designed to deliver future generations of semiconductors with enhanced speed, reduced physical footprint, and improved power efficiency.