Samsung advanced semiconductor roadmap spans facilities across Pyeongtaek, Hwaseong, Giheung, and a new U.S. campus in Taylor, with yield challenges complicating a $16.5 billion deal tied to Tesla.

Samsung’s foundry operations span two countries and four campuses, anchored by Korean facilities in Pyeongtaek, Hwaseong, and Giheung, alongside a new site in Taylor, Texas. The company began mass-producing its first-generation 2nm process in 2025, relocated equipment to its long-delayed Taylor fab in April, and secured Tesla’s AI6 processor under a $16.5 billion contract signed in July 2025. Despite these milestones, Samsung’s foundry remains roughly ten times smaller than TSMC’s by revenue, with advanced-node yields still constraining profitability. Samsung confirmed the 2nm milestone in its fourth-quarter 2025 earnings report, which also marked the foundry unit’s return toward profitability driven by HBM4 logic-die orders. Nevertheless, the unit trails TSMC approximately 11:1 in revenue, and reported 2nm yields hover near 55%, falling short of the threshold required for profitable high-volume manufacturing.

What distinguishes Samsung from TSMC is not fabrication capacity or customer acquisition, but yield performance. Samsung has been able to absorb the financial burden of this gap because its foundry unit operates within the Device Solutions division, subsidized by a memory business posting record profits. The company does not publish a standalone foundry profit-and-loss statement, granting the operation years of runway that a pure-play foundry would lack. The Taylor project serves as both the centerpiece of Samsung’s roadmap and its most persistent challenge. The full campus—encompassing two fabs, an advanced packaging facility, and an R&D center—is valued at approximately $44 billion, with over $37 billion tied to U.S. government funding. Samsung’s CHIPS Act award was reduced from up to $6.4 billion to up to $4.745 billion as the project scope narrowed, while Texas added roughly $250 million in state incentives last September. Construction stalled through 2024 and into 2025, initially attributed to a lack of committed customers and yield issues on the targeted node. Following an equipment move-in ceremony in April, the site will now install a third-generation SF2P+ variant of the 2nm process. Trial production is targeted for late 2026, with full mass production slated for 2027 and a capacity goal of approximately 50,000 wafer starts per month. Tesla’s AI6 chip will anchor the facility under an eight-year agreement running through 2033. However, the AI6 design has reportedly slipped by six months due to a delayed engineering run on Samsung’s 2nm line, pushing volume production toward late 2027.

Pyeongtaek remains Samsung’s largest production base, organized across lines designated P1 through P5. Near-term activity centers on P4, where Samsung has accelerated equipment installation to deploy an HBM4 base-die line on its 1c-class DRAM platform, and on P5, the site’s final planned fab. After construction was previously halted, P5 is now advancing amid surging AI memory demand, carrying a reported investment of nearly 90 trillion won and targeting production by 2029. This expansion occurs against a backdrop of broader capital expenditure restraint. Throughout 2024 and 2025, Samsung sharply curtailed foundry spending and reviewed potential pauses on both Pyeongtaek and Taylor projects as losses mounted. Foundry utilization dipped to around 50% in the second half of 2024 before recovering as clients returned. Process development continues out of Hwaseong’s EUV line, while the newer Giheung NRD-K research complex—a roughly 20 trillion won investment extending to 2030—focuses exclusively on advanced-node R&D. Samsung deployed an ASML High-NA EUV research tool, the Twinscan EXE:5000, at Hwaseong for development purposes and is acquiring two mass-production-class EXE:5200 systems. Originally scheduled for delivery in the first half of this year, these tools are aimed at the SF1.4 node and next-generation DRAM. However, logic-side plans have shifted: Samsung’s updated roadmap retains SF1.4 on Low-NA tooling and reserves High-NA EUV for the 1nm generation. As this research infrastructure feeds production fabs, its output will dictate how rapidly Samsung stabilizes 2nm and transitions to 1.4nm.

Samsung’s 2nm family spans the first-generation SF2 node, now in mass production, through the current-year SF2P rollout, the SF2P+ variant heading to Taylor, and SF2Z, which incorporates backside power delivery and targets mass production in 2027. The 1.4nm SF1.4 node was initially slated for 2027 mass production when announced at the 2022 Foundry Forum. That timeline has officially shifted to 2029, per an updated roadmap presented at the August 2026 Next-Generation Lithography + Patterning Conference, committing the company to three additional years of refining the SF2 architecture before advancing to the next node. The same presentation provided Samsung’s first confirmation of High-NA EUV’s production entry point: not at 2nm or 1.4nm, but at the 1nm-class SF1A node around 2030. “We believe High-NA EUV will become necessary from A10 and below,” Chang Min Park, Master VP of Technology at Samsung Electronics, told the conference, noting that the tooling requires further refinement before it can support mass production at larger nodes. SF1A will launch alongside SF1.4+, an enhanced 1.4nm variant that maintains proven Low-NA processes, offering customers concerned about High-NA’s smaller exposure field and higher costs a familiar alternative. Ultimately, roadmaps depend on yields, and Samsung faces the same reality. While first-generation 2nm yields climbed throughout 2025, they remained near 55% as of April, below the level needed for profitable high-volume output. Reports suggest Qualcomm may redirect work to TSMC as a result. These figures represent industry estimates rather than official disclosures, yet they consistently point to yield—not capacity or customer demand—as Samsung’s primary bottleneck. To remain competitive, Samsung has aggressively discounted pricing, cutting 2nm wafer costs to approximately $20,000, undercutting TSMC by roughly 33%. While this discount attracts price-sensitive clients, it severely compresses margins on a node already operating below break-even yields. Funding this combination of price undercutting and yield lag is unsustainable without external support, explaining why the unit’s losses have dictated its recovery pace.

Samsung’s anchor customer for 2nm is its own mobile division. The Exynos 2600, fabricated on SF2, marks the node’s first commercial product and powers the standard Galaxy S26 and S26+ models. However, the Galaxy S26 Ultra utilizes Qualcomm’s Snapdragon SoCs globally, and Exynos chips account for only an estimated quarter to a third of S26 production due to yield constraints. A successor, the Exynos 2700 built on SF2P, is in development for the Galaxy S27, with mass production targeted for the second half of this year. Leveraging internal processors to validate a node before courting external clients mirrors Samsung’s strategy during the 3nm transition. External 2nm customers remain limited. Japanese AI firm Preferred Networks stands as the clearest early adopter, confirmed as a turnkey client for SF2 combined with 2.5D packaging on AI accelerators. Tesla’s AI6 represents the most prominent external commitment, alongside unconfirmed reports of a 2nm CPU order from North American fabless designer AMD and advanced-stage discussions with Qualcomm regarding future Snapdragon designs. Samsung’s strongest competitive advantage lies in memory rather than logic. The company shipped the industry’s first commercial HBM4 in February, operating at 11.7 Gbps per pin against an 8 Gbps JEDEC baseline, with speeds extendable to 13 Gbps and per-stack bandwidth reaching up to 3.3 TB/s. The logic base die supporting these stacks is manufactured on Samsung’s proprietary 4nm foundry process, enabling the company to source base dies internally rather than purchasing them from TSMC like several competitors, and leveraging that vertical integration to reinforce its foundry competitiveness.