Arm showcased its AGI data center CPU at Hot Chips 2026, marking its first complete commercial CPU design built around Neoverse V3 cores.

Continuing coverage of the second CPU session at Hot Chips 2026, Arm presented its first complete commercial CPU design, the AGI, targeting the AI and data center markets. Built around Arm’s latest Neoverse V3 CPU cores, the AGI marks a strategic shift for the long-standing chip IP designer: rather than licensing IP alone, Arm is now offering a fully integrated CPU directly to server vendors. This move grants the company unprecedented control over its product trajectory and manufacturing destiny.

While the AGI represents Arm’s inaugural in-house silicon, the company’s expertise in processor design is well established. The Neoverse V architecture family has reached its third generation, following the V2 iteration that powered numerous commercial and hyperscaler internal chips. The AGI serves as a showcase of Arm’s accumulated technologies, integrating up to 136 Neoverse V3 cores per chip to drive next-generation agentic AI servers. Over the years, Arm’s engineering focus has evolved from pure IP development to designing entire compute subsystem (CSS) blocks, culminating in this first commercial-grade silicon release. The Neoverse V3 core itself prioritizes a balance between performance and power efficiency, featuring a private 2MB L2 cache and a 128-bit SVE2 SIMD unit.

To support this dense core count, Arm developed the CMN-S3 interconnect mesh, engineered to meet several key objectives: scaling across a large number of CPU cores, delivering substantial memory bandwidth, and supporting extensive I/O bandwidth for PCIe and peripheral devices. The AGI SoC is constructed from two Neoverse V3-based chiplets, a decision driven by physical platform limitations and yield optimization. Each chiplet houses 70 CPU cores distributed across 35 compute tiles, with two cores per tile. These tiles are arranged in a mesh topology that strategically balances processing units with memory, I/O, and die-to-die (D2D) subsystems. A dedicated D2D link connects the two chiplets, operating at 32Gbps per lane to prevent bottlenecks and ensure the dual-chiplet package functions nearly identically to a monolithic die.

Arm selected TSMC’s N3P process node for the AGI chiplets, citing its proven performance and manufacturing maturity. The decision reflects a deliberate avoidance of the newer N2 node, which posed early-yield risks and potential access constraints at this stage. Each chiplet houses over 50 billion transistors. While the hardware supports 144 cores, four are reserved for die harvesting, leaving a maximum of 136 active Neoverse V3 cores per SoC. Arm deliberately allocated fewer gates and less die area to clock speed enhancements, prioritizing energy efficiency over higher frequencies. In practice, 64-core variants will run at a nominal 3.5GHz with boosts up to 3.7GHz, while higher-density configurations operate at a nominal 3.2GHz with a maximum boost of 3.5GHz.

The AGI delivers aggregate memory throughput exceeding 800GB/s, equating to approximately 6GB/s per core, within a 300W thermal design power (TDP). Both IPC and frequency targets align with production specifications, and latency remains low in a NUMA-2 configuration. Memory capacity is handled by a 12-channel DDR5 subsystem capable of 845GB/s of bandwidth using DDR5-8800 modules. The system maintains peak speeds at 1DPC, dropping to DDR5-6400 at 2DPC. Arm explicitly designed the I/O subsystem to match memory bandwidth, utilizing six I/O controllers that provide 96 PCIe Gen6 lanes alongside six Gen4 utility lanes. The hardware supports bifurcation down to 4×4 configurations and includes full CXL 3.0 compatibility, including Type3 devices.

Within the memory subsystem, Arm employs MPAM resource partitioning to maintain consistent performance and mitigate starvation, complemented by hardware support for programmable page policies. The D2D interface leverages UCIe standards via two x16 modules, delivering 1TB of bidirectional bandwidth between dies. This exceeds memory bandwidth capacity specifically to sustain high performance in NUMA-1 mode. During the presentation, Arm also unveiled a reference server design, though it emphasized that multiple vendor implementations will follow to address diverse workloads ranging from rack-scale systems to traditional commercial servers. While software ecosystem development was not the primary focus of the session, Arm acknowledged its critical role in the broader deployment strategy.

The AGI marks the beginning of Arm’s long-term commitment to in-house data center silicon. The company outlined an extensive SoC roadmap detailing subsequent generations of server processors, reinforcing its strategic pivot toward direct hardware manufacturing and end-to-end control of the AI infrastructure stack.