HBC and HBF memory technologies emerge as next-generation successors to HBM, addressing capacity constraints.
The global semiconductor industry is racing to develop a successor to 'High Bandwidth Memory' (HBM)—what has become the defining memory architecture of the AI era. HBM, which stacks DRAM vertically to maximize data processing speed, has been central to AI training workloads. Yet as demand for AI inference—where deployed models answer real-world queries—accelerates, the industry is competing to define next-generation standards that prioritize power efficiency and reduced data movement.
Qualcomm recently unveiled 'High Bandwidth Compute' (HBC), a memory design that stacks multiple low-power DRAM (LPDDR) chips atop an accelerator dedicated to AI computation. Unlike traditional HBM, which requires constant data exchange with a graphics processing unit at enormous power cost, HBC processes portions of computation near the memory itself and transmits only essential results. Qualcomm claims HBC delivers six times higher bandwidth per watt than HBM.
NVIDIA has taken a different approach with 'SOCAMM' (Small Outline Compression Attached Memory Module)—a modularized LPDDR-based design adapted for server environments. SOCAMM borrows efficiency gains from smartphone memory while delivering superior power efficiency compared to conventional server DRAM. NVIDIA's next-generation GPU, Rubin, will retain HBM4, but its CPU, Vera, will adopt SOCAMM2, supplied by Samsung Electronics and SK Hynix.
'High Bandwidth Flash' (HBF) represents an alternative paradigm entirely. Rather than stacking DRAM, HBF stacks NAND flash memory—non-volatile storage that retains data without power. Though slower than DRAM, NAND offers vastly higher capacity at lower cost, making it suitable for storing large volumes of frequently accessed AI data near servers. Where HBM functions as a rapid-access workbench, HBF serves as a nearby storage cabinet. SanDisk leads HBF standardization efforts, with SK Hynix participating.
Intel and CaiMemory (a SoftBank subsidiary) are developing 'Z-Angle Memory' (ZAM) as an HBM alternative. Like HBM, ZAM stacks DRAM vertically, but routes data pathways at oblique angles rather than straight channels—reducing power consumption and heat generation.
A parallel research direction explores 'Processing-in-Memory' (PIM), which integrates computational functions directly into memory semiconductors, allowing memory to perform partial calculations on data in place. Samsung Electronics and SK Hynix are advancing LPDDR-based PIM implementations.
According to semiconductor industry observers, the transition from HBM-centric training to inference-focused systems is reshaping memory architecture. "While HBM was the core memory for the AI training era, the inference era prioritizes power efficiency and minimizing data movement. The next HBM won't be a single memory standard but will emerge from competition in designing entire systems that move data less and process it closer."