Synopsys launches hardware-accelerated verification tools purpose-built for AI chip design and acceleration.

Synopsys, Inc. announced advancements across its hardware-assisted verification (HAV) portfolio on March 11, 2026, introducing new hardware platforms and capabilities to support AI chip verification demands from the data center to the edge. The company's HAV platforms, powered by software-defined capabilities, set new performance, scalability, and use case benchmarks for verifying sophisticated multi-die and AI chips as design complexity and time-to-market requirements intensify.

AI chip verification complexity is escalating rapidly as large language models continue to double in size roughly every four months, and interface data rates advance at a 2x rate every three years. Edge AI architectures are driving aggressive throughput, latency, and power-efficiency targets that expand the design and validation workload. The industry requires HAV solutions to support broader application coverage and run quadrillions of verification cycles to enable first-time-right silicon and seamless integration of heterogeneous AI systems.

The latest advancements include breakthrough performance and capacity through the ZeBu Server 5—described as the industry's highest capacity-scalable emulation platform supporting complex mega designs for data center AI training and inference, GPU, custom accelerators, and networking IPU/DPU workloads—and modular HAPS enabling the largest prototypes for software development. New platforms include the HAPS-200 12 FPGA and ZeBu-200 12 FPGA systems, which address complexity and high-performance requirements for data center, mobile, client, server, consumer, and edge AI applications, delivering 2x higher capacity compared to previous 6 FPGA platforms while utilizing the AMD Versal Premium VP1902 adaptive SoCs with EP-Ready Hardware-enabled configurability. Synopsys also introduced the HAPS-200 1 FPGA platform as a desktop system for IP verification and software bring-up using Synopsys Interface Prototyping Kits.

Software-defined HAV capabilities extend system lifetime value through continuous software improvements delivering compounding performance gains and increased debug productivity. The portfolio now supports industry-first Hardware-Assisted Test Solutions—test automation capabilities allowing teams to stress corner cases for processor, memory, and I/O subsystems and validate full-system coherency under realistic workloads before silicon is ready. Real-Number Models (RNM) emulation enables fast, scalable abstraction of analog behavior for faster software bring-up, while new fault emulation capabilities enable scalable fault injection and analysis across RTL simulation, emulation, and prototyping for safety-critical and high-reliability designs.

AMD's Salil Raje, Senior Vice President and General Manager of Adaptive and Embedded Computing Group, stated that "Hardware-assisted verification is no longer optional. It is critical to meeting aggressive time-to-market goals and ensuring silicon readiness," emphasizing that "through joint optimization of Synopsys ZeBu with the AMD Vivado software stack, and by leveraging AMD EPYC processors for compute acceleration, we are reducing compile times and helping customers move to accurate system models faster." NVIDIA's Narendra Konda, Vice President of Hardware Engineering, said that "Synopsys' software-defined hardware-assisted verification and the new HAPS-200 12 FPGA systems are accelerating our system-level verification and validation, helping us deliver complex AI platforms on aggressive schedules," and that "Synopsys modular hardware-assisted verification enables deeper collaboration across our ecosystem." Synopsys Chief Product Management Officer Ravi Subramanian noted that "as AI becomes more pervasive across almost every industry and products are now workload-optimized and silicon-powered, building high confidence early that the workloads are running to spec on the silicon under development is critical," and that the company's "software-defined, hardware-assisted verification solutions deliver continuous innovation" as "a powerful force multiplier to scale verification productivity and meet the growing demand for pre-silicon development across industries."