Alphawave completed tape-out of a UCIe (Universal Chiplet Interconnect Express) multi-interface chiplet design.

Alphawave Semi has taped-out an IO chiplet on TSMC's 7nm process that the company claims to be the industry's first to cover UCIe (universal chiplet interconnect express revision 1.1) Ethernet, PCIe and CXL in a single design.

The chiplet delivers a total bandwidth of up to 1.6Tbit/s and supports up to 16 lanes of multi-standard PHY supporting PCIe 6.0, CXL 3.x and 800G Ethernet in a combination of mixed operating modes. The 24Gbps UCIe silicon platform integrates multiple connectivity standards into a flexible, scalable solution for datacenter applications.

According to Alphawave general manager Mohit Gupta, "Our hyperscaler and datacenter infrastructure customers can mix and match custom SoCs with our I/O connectivity or memory expansion chiplets, providing flexibility and scalability for their systems." This approach enables customers to combine standard chiplets with Alphawave's modular IO and memory expansion offerings to build tailored solutions for their specific infrastructure needs.

The chiplet was unveiled at the 2024 Chiplet Summit in Santa Clara, marking a significant milestone in the evolution of chiplet-based architecture for hyperscale and datacenter infrastructure.