Broadcom and FuriosaAI are investing in Ethernet-based AI fabric networks for data center interconnect.

Broadcom and South Korean AI infrastructure startup FuriosaAI announced a partnership to build a rack-scale inference platform designed to push AI infrastructure beyond GPU-centric architectures. The partnership pairs FuriosaAI's third-generation Tensor Contraction Processor architecture with Broadcom's networking, packaging, and interconnect technologies to create a multi-die chiplet inference system for hyperscale AI deployments. According to Alex Liu, SVP of product and business at FuriosaAI, the effort represents "a strategic partnership that moves beyond a traditional ASIC partnership," combining Furiosa's accelerator architecture with Broadcom packaging, Ethernet switching, and PCIe technologies to build infrastructure capable of scaling "compute clusters to thousands of nodes." The platform integrates Furiosa's inference architecture with Broadcom Ethernet fabrics, PCIe technologies, advanced packaging capabilities, and AI infrastructure IP to scale inference clusters across thousands of nodes.

The announcement arrives as AI infrastructure operators increasingly confront a new problem: inference workloads are beginning to scale faster than the training environments that initially drove the generative AI boom. The partnership extends Furiosa's broader strategy around vertically integrated inference infrastructure, which the company has pursued as part of a larger push to reduce dependence on NVIDIA's software ecosystem. Furiosa CEO June Paik previously framed this effort by saying, "The challenge is for us to replace this CUDA engine with our own software stack." The Broadcom partnership expands that strategy from single-server optimization into rack-scale networking and cluster architecture.

The shift reflects changing constraints in large-scale inference deployment. While model training depends heavily on tightly coupled GPU clusters and proprietary interconnects like NVLink, inference infrastructure at production scale faces different requirements: power density, networking efficiency, memory bandwidth, latency, and token throughput. Ron Westfall, VP and practice lead for networking and infrastructure at HyperFrame Research, explained that "large-scale inference shifts the bottleneck toward optimizing TCO, memory bandwidth, and power consumption per token." Charlie Kawwas, president of Broadcom's Semiconductor Solutions Group, stated that "inference performance is no longer defined solely by raw compute. It is increasingly a function of data reuse and communication efficiency across servers and racks."

Technically, Furiosa's third-generation accelerator will use a 2nm compute die paired with dual-layer HBM4/4E memory and Broadcom packaging technology to integrate multiple silicon dies into a single system-on-chip platform. Broadcom's Ethernet and PCIe technologies will provide the high-bandwidth rack-scale connectivity required to scale large inference clusters. The architecture signals growing industry momentum behind Ethernet-based AI infrastructure as an alternative to proprietary GPU fabrics. Earlier this year, Broadcom CEO Hock Tan said the company saw a path to delivering more than $100 billion in AI chip revenue by 2027, driven by hyperscaler demand for custom silicon and diversified AI architectures beyond traditional GPU deployments.

Furiosa argues inference infrastructure requires fundamentally different architectural assumptions than GPU-based training systems. "By focusing on high-bandwidth data movement rather than the thread management required by GPUs, the chip will deliver higher performance-per-watt and greater token density than state-of-the-art GPUs," the company stated. Westfall reinforced this systems-level perspective, noting that "optimizing large-scale token generation is no longer just a silicon challenge, but a holistic systems-engineering problem driven by the network itself," and that "optimizing networking efficiency and rack-scale interconnectivity is now just as vital to inference economics as raw silicon performance."