Friday, August 7, 2026
DarkSubscribe
AI Infrastructure · News & Analysis
HomeChips & HardwareReport
Chips & Hardware · Report

AMD discloses its enterprise CPU and GPU roadmap including new Venice and Verano CPUs and Helios and CDNA GPU generations.

AMD's roadmap directly competes with NVIDIA for data center GPU market share and shows AMD's commitment to high-performance AI accelerators.
Trade pressSlicast · March 23, 2026 · Global · Source: tomshardware.com
importance 80

AMD's position in the data center market has undergone a remarkable transformation in recent years, growing from an underdog supplying less than 1% of server CPUs in 2017 to commanding nearly 29% of the server CPU market as of late 2025. Following this period of aggressive expansion, AMD is refining its market approach by implementing annual cadences for new product releases across both its AI and traditional data center CPU lines.

Over the next 24 months, AMD plans to launch a series of major products. In 2026, the company will introduce the Zen 6-based EPYC Venice CPU with up to 256 cores, along with the Instinct MI400-series AI and HPC accelerators that will power the Helios rack-scale solution for AI. In 2027, AMD will release the EPYC Verano processor and the Instinct MI500-series AI and HPC GPUs, which will serve as the foundation for the company's next-generation rack-scale AI system.

The EPYC Venice processor represents a significant generational advance as AMD's first data center design manufactured on TSMC's N2 (2nm-class) process technology. With up to 256 high-performance Zen 6 cores, Venice achieves a 33% increase over the current EPYC Turin processors that feature up to 192 Zen 5c compact cores. The new design adopts the all-new SP7 form factor to accommodate more compute complex dies, increase memory channels, enhance I/O capabilities, and boost peak power delivery. Memory bandwidth will increase dramatically to 1.6 TB/s per-socket throughput, more than doubling the 614 GB/s available on current EPYC CPUs, likely through advanced memory modules such as MR-DIMM or MCR-DIMM. CPU-to-GPU bandwidth is planned to double, likely through PCIe 6.0, which can deliver roughly 128 GB/s of bidirectional bandwidth per link. With as many as 128 PCIe lanes, Venice will substantially increase data movement between CPUs and accelerators. AMD claims the EPYC Venice processor will deliver up to 70% higher performance compared with the existing EPYC 9005-series, and has also teased a Venice-X variant with extra L3 cache for sovereign AI and HPC platforms featuring the Instinct MI430X and MI440 accelerators.

The 2027 EPYC Verano processor remains less clearly defined, as AMD has not officially designated it as a seventh-generation EPYC offering or confirmed whether it will be based on Zen 7, Zen 6, or a Zen 6+ variant. Verano's planned introduction coincides with the ramp of TSMC's A16 fabrication process, which is expected to enter high-volume production in late 2026 and will feature backside power delivery to improve power distribution and efficiency—benefits particularly valuable for large datacenter CPUs and AI accelerators. While AMD has not officially confirmed the process technology underlying its 2027 server products, the roadmap timing and the advantages of backside power delivery for high-current compute silicon suggest that AMD's 2027 data center products may be built on A16.

Read the original
AMD discloses its enterprise CPU and GPU… · Slicast