TSMC is actively advancing CoPoS (panel-level) packaging technology to replace CoWoS in response to growing computing demands, with glass-based chip substrates becoming a key focus.

Growing artificial intelligence and computing demands require next-generation packaging technologies. Intel and TSMC are actively advancing this objective, with glass-based chip substrates becoming an important component of their future development roadmaps.

According to recent reports from Taiwan Business Times, TSMC is now actively transitioning to CoPoS (Chip-on-Panel-on-Substrate) packaging technology to replace CoWoS (Chip-on-Wafer-on-Substrate) packaging. To achieve this goal, glass-based chip substrates play a crucial role, which is why the Taiwan-based semiconductor manufacturer has accelerated the development and mass production timeline for this technology.

TSMC is actively advancing CoPoS and accelerating ecosystem development. To overcome the existing physical limitations of CoWoS, the ability to accelerate production yield rates with glass-based chip substrates is a key factor. The Taiwan-based manufacturer is actively developing critical technologies for glass-based chip substrates and CoPoS process equipment, aiming to lead in the advanced packaging field for AI chips.

The advantages of CoPoS over CoWoS have been well documented. Transitioning to larger square or rectangular wafers (or panels) produces more chips and memory modules compared to CoWoS's circular wafer design.

Standard CoWoS wafer sizes are approximately 300 millimeters, while CoPoS wafers can reach 750×620 millimeters (TSMC will also introduce 310×310 and 515×510 millimeter panel-level wafers, as previously disclosed). This not only allows for larger compute chips but also delivers higher yields (improved wafer/chip utilization rates), with per-unit-area costs reduced by 20-30%.

Combined with advanced packaging solutions, panel-level packaging enables large-scale multi-chip integration. From a cost perspective, silicon is replaced by glass, ensuring high-yield and cost-effective production. TSMC's first CoPoS pilot production line has been constructed, with Taiwan-based experts stating that CoPoS utilizing glass-based chip substrates is critical for bridging supply-demand gaps in next-generation high-end chips.

Key points regarding TSMC's next-generation advanced packaging CoPoS (omitting publicly available technical details): 1. CoPoS is expected to enter mass production in the second half of 2028. Its design objective is to improve the economics of ultra-large packages (exceeding 9.5× photolithographic reticle size classes)…

TSMC plans to initiate CoPoS wafer mass production next year, with pilot production beginning in 2027 and mass production targeted for 2028. The timeline for CoPoS utilizing glass-based chip substrates is set for 2030 and beyond. TSMC's Arizona facility is expected to play a significant role in CoPoS production during 2029-2030.

Analyzing TSMC's glass-based chip substrate slide: On June 11, at Japan's JPCA Show 2026 exhibition, TSMC delivered a presentation with approximately 40 slides titled "Advanced Packaging Technology Essential for AI Evolution." One slide from the presentation was titled…pic.twitter.com/QegDEOM6Nd

Meanwhile, TSMC also plans to utilize glass-based substrate technology for CoWoS, a technology currently under development that provides various improvements including cost reduction and enhanced chip utilization rates. TSMC is collaborating with Japan's Ibiden and Taiwan's Innolux to develop its glass-based chip substrate technology, utilizing a 3-layer design with glass core sandwiched between two ABF layers.

CoPoS employs panel-level packaging, transforming circular to square configuration, which can significantly increase material utilization of traditional 12-inch circular wafers from below 70% to over 90%, addressing geometric waste and cost escalation issues caused by maximum photomask size constraints for ultra-large AI chips after 2028.

These timelines are consistent with what Intel and its partners have already mentioned. Executives of Ampere Computing have stated that Intel's glass substrate technology will be ready for commercial deployment within three years, with advanced panel-level solutions featuring co-packaged optics already demonstrated. Intel plans to make its Rio Rancho facility the "crown jewel" for the production of these glass-based chip substrate packaging technologies.

TSMC and Intel will be the two major players in the glass-based chip substrate field in the future. Intel's foundry business success and its advanced packaging solutions such as EMIB have already gained strong recognition from major customers, and with its accelerated advancement in the glass-based chip substrate field, the company will become an important participant in the foundry business.

Meanwhile, reports have indicated that AMD will become a key customer of TSMC, adopting its FOPLP (Fan-Out Panel-Level Packaging) technology and 1.4nm process node for its client-focused Zen 7 product line. The applications of FOPLP and CoPoS will extend beyond client applications and play a greater role in AI and compute-oriented data center markets.