Samsung outlined its roadmap for evolving the HBM base die at Hot Chips 2026 to optimize package area utilization for more efficient compute integration.
At Hot Chips 2026, Samsung presented “Evolving HBM Base Die,” outlining its strategy to transform the base die of high-bandwidth memory from a passive interposer into a highly capable component. This report covers the session live; please excuse any minor typographical errors.
HBM divides its workload between DRAM core dies stacked above and a base die positioned beneath. Samsung designates the stacked memory layers as C-dies, while the base die (B-die) houses the physical layer (PHY) and through-silicon vias (TSVs) that establish the communication channel to the compute die. These stacks typically consist of four, eight, twelve, or sixteen C-dies mounted on the base die. A structural diagram is provided for reference.
HBM bandwidth and capacity have grown steadily since inception. Samsung’s historical data traces maximum capacity from approximately 1 GB and 1 TB/s in the original HBM generation to an HBM5 specification exceeding 60 GB and 6 TB/s. While capacity has increased, rising bandwidth demands are the primary driver forcing fundamental architectural changes in the base die.
Several physical constraints throttle further bandwidth scaling. Samsung identifies limitations in TSV counts and pitch across both the C-die stack and the base die, alongside the I/O count and operating speed of the PHY embedded within the B-die. The accompanying charts illustrate how TSV and DQ counts scale against pitch and area across generations, highlighting where architectural pressure intensifies.
While C-die manufacturing remains on DRAM-class nodes, the base die is transitioning toward advanced logic processes. Samsung’s trend analysis shows the B-die migrating from legacy logic nodes to 4 nm starting with HBM4, significantly narrowing the process gap relative to the XPU system-on-chip. Although energy efficiency improves with node advancement, total package power (MPGA) continues to rise, prompting Samsung to emphasize that integrating advanced logic into the B-die becomes essential from HBM4 onward.
Samsung applied its D1c DRAM process alongside a 4 nm logic node to HBM4, prioritizing power reduction and active area minimization. This initiative marks the beginning of genuine DRAM and advanced logic integration. Performance traces across process nodes demonstrate that both TSV-to-PHY repeater power consumption and signal delay decrease as the logic node advances.
Standard HBM (sHBM) confines the B-die to fundamental data routing and test-path functions. In contrast, custom HBM (cHBM) leverages advanced logic to construct a more system-on-chip-like base die while retaining compatibility with standard C-die stacks. We have previously examined custom HBM architectures explored by non-memory vendors such as Marvell.
Conventional scaling pathways are approaching physical boundaries. Node shrinks are decelerating, monolithic dies are nearing reticle limits, and multi-chiplet interposers are constrained by physical dimensions. Samsung’s response is to utilize the B-die’s existing advanced logic capabilities to offload select functions from the XPU.
On conventional sHBM designs, the PHY occupies the largest footprint on the base die. Samsung replaces this traditional PHY with a die-to-die (D2D) interface built on advanced logic, which reduces the physical footprint, shortens signal channels, and enhances energy efficiency. The reclaimed silicon area enables XPU expansion, as demonstrated in comparative floorplan layouts.
From HBM2 through sHBM4, PHY footprints and channel depths continuously expanded to support higher bandwidth. Advanced logic sharply reduces PHY and D2D area requirements from HBM4 into HBM5 by concentrating greater power output into a compact footprint. While shorter channels reduce energy per bit, the resulting increase in power density introduces localized thermal hotspots.
To address this thermal pressure, Samsung proposes a Heat Path Block (HPB), developed using insights from its cHBM4 design. Achieving PHY coverage above 50 percent reduces peak temperatures by more than 35 percent—a critical improvement as I/O speeds roughly double from sHBM4E to sHBM5 and power density escalates from 0.5 W/mm² to over 2.0 W/mm².
Once sufficient space is available, Samsung begins migrating XPU logic onto the base die, with the memory controller serving as the primary target. Relocating the memory controller frees valuable XPU silicon, and Samsung notes that the associated thermal impact remains manageable. Industry efforts are already underway to port conventional HBM memory controllers into cHBM architectures.
Integrating SRAM onto the base die also enhances reliability. Samsung’s SRAM-based cell repair mechanism utilizes otherwise idle B-die space to decode and redirect failed-cell addresses with fine granularity, distributing repair capacity across multiple channels. Compared to conventional approaches that rely on limited spare resources within the C-die, this method provides substantially larger and more flexible repair resources on the B-die.
Phase one of this evolution leaves substantial silicon capacity unutilized. Because the overall HBM footprint is primarily dictated by the C-die stack and most of the sHBM base die consists of passive routing, significant real estate remains even after relocating the memory controller. This unused B-die area forms the foundation for phase two’s expanded functionality.
Custom HBM introduces system-on-chip-level reliability, availability, and serviceability (RAS) features directly into the base die—capabilities absent in standard HBM. Samsung integrates thermal, voltage, process, and aging sensors for real-time telemetry, alongside on-chip self-test mechanisms such as on-die automated test equipment (ATE) and pattern generators. These enhancements improve test coverage and manufacturing yield, clearly distinguishing the cHBM architecture from sHBM.
Capacity requirements are expanding at a pace comparable to bandwidth growth. Samsung highlights that context windows are increasing by approximately 30 times annually, driving massive demand for KV cache memory. Consequently, long-term memory storage and retrieval have emerged as critical bottlenecks for next-generation AI models, pushing AI SoC development toward higher capacity rather than bandwidth alone.
One approach to augmenting capacity involves connecting external memory directly to the base die. Samsung utilizes the outer perimeter of the B-die to attach external memory through dedicated PHYs and controllers integrated directly onto the chip. This configuration delivers higher bandwidth and lower latency compared to conventional PCIe-based expansion solutions.
Samsung also identifies opportunities to offload computational tasks onto the base die. Processing elements integrated into the B-die can handle partial workloads from the XPU SoC, reducing die-to-die bandwidth requirements and lowering overall power and thermal overhead. However, limited silicon area and rising thermal density from these processing elements remain key engineering challenges.
By integrating processing elements into the base die, Samsung advances toward tighter 2.5D system architectures. Advanced HBM (aHBM) offloads XPU computations to these embedded processing elements, minimizing data movement across the interposer. Samsung characterizes the resulting power efficiency improvements as a system-level breakthrough.
Phase three moves entirely beyond the interposer. Samsung argues the industry is transitioning toward tightly coupled AI memory architectures, where maximizing tokens per second within strict power envelopes defines the inference challenge. zHBM addresses this requirement through true three-dimensional vertical integration of the XPU and the C-die stack, effectively eliminating the 2.5D interposer.
zHBM fundamentally alters HBM’s physical architecture. Distributed input/output interfaces shorten internal data travel distances, while the true three-dimensional structure removes conventional two-dimensional interfaces such as the HBM PHY and D2D links. This arrangement is specifically engineered to achieve ultra-low power consumption.
Power efficiency represents zHBM’s primary advantage. Eliminating SERDES circuits and data-alignment overhead drastically reduces I/O power consumption. According to Samsung’s system-level estimates, deploying four zHBM stacks within a single-package module alongside a 1,200-watt GPU yields a substantial bandwidth increase while conserving approximately 100 watts of power.
Realizing zHBM relies on two foundational technologies: wafer-on-wafer bonding and hybrid copper bonding, which enable ultra-high I/O density. Samsung emphasizes that a unified system-on-chip and DRAM design and verification flow is essential for successful co-architecture development. The referenced figure outlines the wafer-on-wafer bonding sequence alongside the integrated design workflow that co-develops the DRAM C-die and XPU.
Samsung concludes by framing a clear three-phase roadmap. Applying advanced logic to the base die unlocks architectural flexibility that enables function offloading and optimization in phase one, expands capabilities in phase two, and converges into true three-dimensional integration with zHBM in phase three. This structured progression—from reclaiming XPU area to ultimately eliminating the interposer—is what Samsung positions as the definitive path forward for HBM base-die evolution.
Collectively, these developments illustrate how Samsung is redefining the HBM base die. No longer a passive interposer, the base die is evolving into a co-processor, fundamentally altering where memory and logic are architected within AI systems. Migrating the memory controller—and eventually processing elements—into HBM provides accelerator vendors with a new substrate for their silicon. While zHBM remains distant, it signals a clear industry trajectory toward stacking compute directly atop DRAM and discarding the interposer entirely. System architects should monitor this shift closely as successive HBM generations reach production. It was a compelling presentation at Hot Chips 2026.