Industry analysis posits that the ability to operate a compute platform is democratizing, making it accessible to new entrants.

Despite fierce competition in the markets for CPUs, GPUs, and XPUs—along with the DRAM, HBM, and flash memory they depend upon—the focus has shifted from feeds, speeds, and price to access to devices themselves. A new market for CPUs is emerging, driven by the specific computing needs of agentic AI, and will come to dominate the installed base of servers within the next few years, even if AI training systems continue to command the larger share of revenues due to their expensive GPUs. This represents a tectonic shift underway, as AMD's top brass have echoed comments made by Intel, indicating not just a resurgence in CPU spending but a fundamental market transformation.

AMD CEO Lisa Su put a stake in the ground at the company's Financial Analyst Day in early November 2025, predicting that the total addressable market for datacenter CPUs would grow at a compound annual growth rate of 18 percent, reaching $60 billion by 2030. This compares to roughly $13 billion to $14 billion in server CPU silicon TAM back in 2015, when Intel accounted for close to 99 percent of shipments and most RISC/Unix and Itanium alternatives were either dead or dying. But in the company's Q1 2026 financial call with Wall Street analysts, Su and her team laid down a new server CPU TAM of $120 billion, raising the CAGR between 2025 and 2030 to 35 percent.

Su identified three distinct slices of the server CPU TAM. The first is general purpose compute; the second is the relatively thin slice of GenAI training and inference where the CPU operates as the head node; and the third—growing exponentially—comprises CPUs devoted entirely to agentic AI work. As Su explained, "You should think about we need all of the accelerators to run these foundational models, and then as these agents do work, they spawn more CPU tasks." The key challenge is ensuring the correct ratio of CPUs to GPUs in deployments. Historically, this ratio was 1:4 or 1:8 configurations, but Su noted that it is now changing and getting closer to 1:1 or even scenarios where there could be more CPUs than GPUs. She emphasized that "it is largely additive to the TAM. And the key is that everyone is now planning and thinking about CPUs at the same time that they are thinking about their accelerator deployments, which is a good thing."

Tracking these ratios is complicated by the specific products being deployed. Nvidia's 72-core "Grace" CPU was paired with the "Hopper" GPU, but with "Blackwell" CPUs, there are two GPUs attached to every CPU—specifically two Blackwell GPU chiplets per socket, yielding a 1:4 ratio. Looking ahead, Nvidia will pair one "Vera" CPU with every pair of "Rubin" GPUs, which amounts to four GPU chiplets in total for a 1:4 ratio later this year, with plans to double up GPU chiplets in 2027 in the Rubin Ultra socket to achieve a 1:8 ratio. With eight compute tiles on the Vera CPU, the effective ratio could approximate 1:1. AMD's "Verano" variation on the "Venice" Epyc 9006 architecture is apparently coming in 2027, with the "Florence" Epyc 9007 processors expected perhaps in late 2027 or early 2028, likely paired with the next generation MI500 series GPUs. The Venice CPUs are slated for later this year.

AMD is positioning itself to capture significant share in this expanding market. As Su stated, "We are clearly feeling like we are seeing significant share gain as we are going into our Turin portfolio that has ramped very nicely. Venice is extremely well positioned, and we are working with customers right now on – beyond Venice and what we are doing in those architectures. So we feel really good about the market as well as our opportunity to grow to greater than 50 percent share of that market."