Synopsys has validated a PCIe 6.0 PHY operating at 64 GT/s within a face-to-face 3D stacked package using a 5nm process, marking a milestone for advanced packaging interconnects.
Synopsys has published silicon results for what it describes as the first 3D PCIe 6.0 test chip. The 5nm PHY is built into a face-to-face stacked package, operating at 64 GT/s per lane and delivering up to 128 GB/s across an eight-lane link using PAM4 signaling. Receiver eyes successfully cleared the standard’s bit error rate requirements. According to the company’s blog post, Synopsys achieved this by deconstructing an existing 2D PCIe 6.0 test chip, adding through-silicon vias (TSVs), and redoing circuit design and signoff against 3D process design kits.
In traditional monolithic chips, PCIe PHYs are positioned at the die perimeter adjacent to package I/O connections, keeping traces to the substrate short to manage attenuation and reflections. A 2.5D package preserves this layout by placing PHYs along the outer edge of the outermost chiplets. Face-to-face hybrid bonding eliminates this option. Because the bottom die is flipped so its redistribution layer bonds directly to the logic die above it, the PCIe PHYs end up facing away from the substrate they must reach. Consequently, signals must travel downward through vias cut into the silicon.
Every TSV passes through active silicon and requires a buffer zone, meaning vias cannot be placed arbitrarily near the PHY. “You rarely drill straight down into the package substrate,” Manmeet Walia, executive director of product management at Synopsys, told Electronic Design. He explained that routing must climb to one of the upper metal layers and reverse direction before descending. Walia noted that electromigration and layout rules change substantially in 3D architectures, and via count becomes a critical tradeoff between maximizing bandwidth and preventing signal corruption. Additionally, customer logic situated over the PHY’s downward path to the substrate presents a challenge that Synopsys expects to address iteratively, design by design. This iterative approach is particularly difficult because PAM4 signaling leaves less margin for error than the NRZ signaling used in PCIe 5.0, as it packs two bits into each symbol.
Other industry players are taking different architectural paths. Fujitsu’s Monaka processor, for example, stacks four N2 compute chiplets carrying 144 Armv9 cores face-to-face onto N5 SRAM chiplets using hybrid copper bonding. Rather than embedding PHYs within the bonded stack, Fujitsu places its memory controllers and the PHYs for its 12 DDR5 channels on a separate, comparatively large I/O die. Meanwhile, the broader ecosystem continues to evolve: SMI reports that Nvidia is driving the consumer PCIe 6.0 roadmap rather than AMD or Intel, while Astera Labs has showcased a 320-lane PCIe 6.0 switch designed for vendor-agnostic scaling in data centers.
Historically, PCIe generations arrived roughly five to seven years apart, but releases have accelerated to approximately every two years. The Gen 8 specification is scheduled for 2028, targeting 256 GT/s per lane. Looking ahead, Walia indicated that a further architectural shift will arrive with 3.5D packaging. In this configuration, PCIe PHYs would be removed entirely from the bottom die and replaced with UCIe interfaces, relocating them to a side chiplet on the interposer that functions as a multi-protocol hub for Ethernet, PCIe, and CXL. Synopsys has not announced a timeline for this transition. Its blog notes that leading-edge customers are currently evaluating angstrom-class process technologies for the top dies in their future stacks.