At Hot Chips 2026, Cerebras unveiled its Nexus system architecture and CS-6 wafer roadmap, which triples rack-scale performance and integrates stacked DRAM.

Cerebras’ SRAM-packed wafer-scale engines (WSEs) have carved out a distinct niche in AI model serving, delivering extremely low-latency, high-throughput inference that powers services such as OpenAI’s ChatGPT-5.6 Sol Ultrafast tier. At Hot Chips 2026, the company unveiled the next two generations of its wafer-scale accelerator roadmap while detailing the performance benefits of its new Nexus rack design for the CS-4 rack-scale system and its three WS-3T wafers.

Integrating a massive coherent processor onto a single silicon slice remains a unique industry achievement, but it inherently carries limitations. AI workloads demand ever-increasing memory capacity due to expanding model sizes—whose memory footprint can be amortized across multiple inference sessions—and increasingly long contexts stored in session-specific KV caches. Traditional GPU vendors have mitigated these pressures by partnering with memory manufacturers to stack higher densities of HBM and allocating more of it per accelerator. However, a wafer-scale design already dedicates 100 percent of its surface area to logic and SRAM. Adding more of any specific resource necessitates sacrificing space allocated to other functions. Since silicon fabrication will continue on 300mm wafers for the foreseeable future, Cerebras must pursue alternative pathways to scale on-chip resources.

To address this, Cerebras announced that its CS-6 system, currently two generations ahead on its roadmap, will transition to stacked architectures. For the first time, the company plans to 3D-stack DRAM atop its logic and SRAM wafer—a move it claims will preserve its inference performance leadership while reducing the overall footprint required per chip. This concurrent reduction in area could enable Cerebras to manufacture a greater number of WSEs, potentially alleviating a critical constraint as the company scales operations amid surging global wafer demand.

In the near term, Cerebras is maximizing its current platform through the CS-4 rack-scale system and its proprietary Nexus rack design. The CS-4 houses three refreshed WS-3T wafers inside self-contained “backpacks” that integrate power delivery, scale-up networking, and liquid cooling into a single pluggable module. Because these modules operate independently, future wafer-scale engines built on this architecture can be upgraded without replacing the entire rack.

Cerebras chief system architect JP Fricker was notably critical of competing scale-up architectures, describing the 5,000 cables used to connect the Rubin NVL72 NVLink domain within each rack as “a mess.” He contrasted this with the Nexus system’s cleaner, less failure-prone approach, which relies on on-die interconnects and self-contained compute modules. The Nexus backpack also disaggregates the WSE’s I/O interfaces from the rest of the assembly. Two interchangeable I/O modules attach to the wafer’s edges, providing RoCE v2 RDMA connections for cross-system interoperability and direct links to other wafers in the rack. This modularity offers a separate upgrade path independent of the core compute wafer.

Power and thermal management are similarly reimagined. Each backpack supports up to ten rack-mounted power delivery units positioned at the front, configurable for varying redundancy levels based on operator requirements. The rack also supplies air cooling for components that require it. By mounting the wafer-scale engines vertically, Cerebras eliminates the need for a traditional PCB or substrate to manage supporting infrastructure. Instead, the backpack connects a large copper busbar directly to the wafer’s rear side. This direct contact minimizes power losses typically incurred when routing electricity through a PCB, a common issue with BGA-mounted GPUs where power delivery circuitry surrounds the die.

Cerebras translates these efficiency gains directly into performance improvements for the WS-3T. The company states that the power savings enabled by the Nexus backpack design allow it to deliver twice the power to the wafer-scale engine compared to previous iterations, resulting in higher clock speeds and up to double the performance of the WS-3. Built on the same base silicon as the WS-3, each WS-3T delivers twice the sparse FP16 petaFLOPS and twice the SRAM memory bandwidth. Nevertheless, the WS-3T remains capped at 44 GB of total memory per wafer, meaning a full CS-4 rack provides only 132 GB. This falls significantly short of the 20.7 TB of HBM in Nvidia’s Vera Rubin NVL72 system and the 31 TB in AMD’s Helios. Cerebras does not publish dense PFLOPS metrics for these engines, likely because its dataflow architecture is specifically optimized to leverage sparsity in ways traditional GPUs generally do not.

To accommodate today’s and tomorrow’s larger models, Cerebras must scale both up and out. Unlike competing rack-scale systems that depend on Ethernet for scale-out, Cerebras can link CS-4 systems together using the same wafer-to-wafer interconnect that ties engines together within a Nexus rack. The company reports 2.4 Tb/s of direct scale-up bandwidth per wafer inside the rack, yielding a total of 7.2 Tb/s of inter-chip bandwidth at 2 μs latencies. Importantly, Cerebras notes that its architecture only requires model activations to traverse between wafer-scale engines. Consequently, the relatively modest bandwidth of the direct wafer link is not a scaling bottleneck when measured against the hundreds of terabytes per second offered by systems like Vera Rubin NVL72 or AMD Helios. (The WSE-3T’s on-die fabric alone provides 53.4 PB/s of bandwidth.)

The CS-4 architecture also establishes the foundation for the next-generation CS-5 accelerator, which will feature new WSE silicon slated for 2027. For smaller models, Cerebras projects the upcoming WSE will deliver up to 10,000 tokens per second per user, while larger frontier models from organizations like DeepSeek or OpenAI could run at approximately 5,000 tokens per second per user. Echoing Nvidia CEO Jensen Huang’s observation that AI agents are impatient, the ability to sustain such high token throughput using specialized accelerators like the CS-4 will likely secure Cerebras a vital niche market. The company intends to continue capitalizing on this advantage alongside its strategic partners at OpenAI and AMD.