AMD and Qualcomm debut advanced chiplet-based packaging technologies for AI accelerators, reducing thermal density and cost.
AMD and Qualcomm have separately introduced new memory packaging technologies designed to address bandwidth bottlenecks in their respective target markets.
AMD unveiled its Versal Premium Gen 2 Memory on Package (MoP) line for industrial applications, which integrates DRAM and a system-on-chip (SoC) in a single package. Qualcomm rolled out High Bandwidth Compute (HBC), a 2.5D-like memory technology targeting AI servers. While these technologies serve different market segments, both enable faster data transfer with reduced latency and claim advantages over existing high-end memory packages, particularly high bandwidth memory (HBM).
**Understanding Packaging**
In semiconductor manufacturing, after chips are fabricated, they move to packaging facilities where processed chips are assembled into IC packages—protective enclosures that also boost chip performance. Packaging companies offer multiple package types tailored to specific applications across automotive, communications, computing, industrial, and increasingly, AI systems.
In AI data centers, systems typically incorporate a powerful AI chip like an accelerator or GPU alongside HBM in a 2.5D package. HBM vertically stacks 8, 12, or more DRAM dies connected by tiny vertical wires called through-silicon vias (TSVs). This architecture enables data transfer between memory and AI chips at high speeds using a 1024-bit memory bus.
Micron, Samsung, and SK Hynix are the primary HBM suppliers. However, DRAM remains in tight supply with escalated prices, constraining HBM availability. TSMC's CoWoS 2.5D packaging technology, widely used for AI chip packaging, faces similar supply pressure. DRAMs are expected to remain scarce through 2027 and beyond.
**Qualcomm's HBC Solution**
Qualcomm introduced its Dragonfly chips for AI data centers—the C1000 CPU, AI300 inference accelerator, and custom silicon—alongside HBC technology. HBC places an AI chip in a 2.5D package with LPDDR DRAM dies stacked and positioned side-by-side, similar to conventional 2.5D HBM configurations but using alternative memory.
Qualcomm claims HBC delivers 6x increase in bandwidth per watt versus HBM and 200x increase in capacity per watt versus SRAM. Jon Peddie, president of Jon Peddie Research, noted that "HBC combines accelerator logic with 3D-stacked DRAM in a tightly coupled package," describing it as "a memory-centric accelerator architecture" that "keeps data closer to compute, reduces movement across external interfaces, and improves bandwidth efficiency."
Peddie highlighted the broader appeal: "Qualcomm's HBC approach puts memory bandwidth, packaging, and power at the center of system design. The inflection point emerges as hyperscalers and enterprises evaluate AI racks through total cost, software portability, and supply resilience. If Qualcomm delivers, AI data centers could support more diverse architectures and reduce dependence on a single software-hardware model." Key remaining questions include packaging, thermals, yield, repair, interconnect topology, and compiler visibility. Commercial sampling of HBC Gen 1 with the AI250 data center rack is expected mid-2027.
**AMD's Memory on Package**
AMD's Versal Premium Gen 2 MoP integrates up to 32GB of LPDDR5X DRAM alongside its Versal SoC, delivering up to 288GB/s of bandwidth in up to 60% less board area. AMD places JEDEC-compatible LPDDR5X devices on the package substrate; the short interconnect distances simplify board design and signal integrity while potentially eliminating months of memory-interface design and validation work.
Targeted at embedded and industrial applications—particularly test and measurement, professional video editing, and VPX systems (rugged, high-performance computing standards used in aerospace, defense, and industrial applications)—AMD's MoP offers 15-plus-year support to shield product roadmaps from HBM's shorter, data-center-driven refresh cycles.